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1995 data sheet the information in this document is subject to change without notice. the mark shows major revised points. description m pd78366a is provided with a high-speed, high-performance cpu and powerful operation functions. unlike the existing m pd78328, m pd78366a is also provided with a high-resolution pwm signal output function which substantially contributes to improving the performance of the inverter control. a prom model, m pd78p368a, is also available. detailed functions, etc. are described in the following users manual. be sure to read the manual to design systems. m pd78366a users manual hardware: u10205e m pd78356 users manual : u12117e features ? internal 16-bit architecture, external 8-bit data bus ? high-speed processing by pipeline control method and high- speed operating clock ? minimum instruction execution time: 125 ns (internal clock: at 16 mhz, external clock: 8 mhz) ? real-time pulse unit for inverter control ? 10-bit resolution a/d converter: 8 channels ? 8-/9-/10-/12-bit resolution variable pwm signal output function: 2 channels ? powerful serial interface: 2 channels ? internal memory: rom: none ( m pd78365a) 24k bytes ( m pd78363a) 32k bytes ( m pd78366a) 48k bytes ( m pd78368a) ram: 768 bytes ( m pd78363a) 2k bytes ( m pd78365a, 78366a, 78368a) application examples ? inverter air conditioner ? factory automation fields, such as industrial robots and machine tools. ordering information part number package internal rom m pd78363agf- -3b9 80-pin plastic qfp (14 20 mm) mask rom m pd78365agf-3b9 80-pin plastic qfp (14 20 mm) none m pd78366agf- -3b9 80-pin plastic qfp (14 20 mm) mask rom m pd78368agf- -3b9 80-pin plastic qfp (14 20 mm) mask rom remark indicates a rom code suffix. unless otherwise specified, the functions and performances of the m pd78366 are described throughout this document. document no. u11109ej2v0ds00 (2nd edition) date published september 1997 n printed in japan mos integrated circuit m pd78363a,78365a,78366a,78368a 16/8-bit single-chip microcontrollers 1995
m pd78363a, 78365a, 78366a, 78368a 2 78k/iii series product development high-speed, multi-function, reinforced interrupt, 10-bit a/d (for control application in oa and fa fields) high-performance cpu, sum-of-products instruction added reinforced timer and a/d, expanded rom and ram pulse output function for inverter control (for hdd) (for control application in oa and fa fields) (for control application in oa and fa fields) (for inverter) a/d, d/a relative instruction added, expanded rom, ram pulse output function for inverter control, expanded rom, ram reinforced timer, a/d added (for control application in automotive appliance) (for inverter) (for camera, hdd) pd78372 subseries pd78356 subseries pd78334 subseries pd78328 subseries pd78352a subseries pd78322 subseries pd78312a subseries pd78361a pd78362a pd78p364a m m m m m m m m m m m m m m m pd78366a subseries m pd78363a pd78365a pd78366a pd78368a pd78p368a
m pd78363a, 78365a, 78366a, 78368a 3 pin configuration (top view) ? 80-pin plastic qfp (14 20 mm) m pd78363agf- -3b9, 78365agf-3b9, 78366agf- -3b9, 78368agf- -3b9 v ss p00/rtp0 p01/rtp1 p02/rtp2 p03/rtp3 p04/pwm0 wdto p07/tclrud v ss x1 x2 mode1 reset p30/t x d0 p31/r x d0 p32/so/sb0 p33/si/sb1 p34/sck p36/r x d1 p35/t x d1 ic v dd p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p41/ad1 p42/ad2 v dd av dd av ref p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 av ss p70/ani0 p40/ad0 v ss p10 p11 p12 p13 p14 p15 p16 p17 v ss mode0 p20/nmi p21/intp0 p22/intp1 p23/intp2 p24/intp3/ti p25/intp4 astb p93 p92 p91/wr p90/rd p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p85/to05 p84/to04 p83/to03 p82/to02 p81/to01 p80/to00 p05/tcud/pwm1 p06/tiud/to40 caution connect the ic pin directly to v ss . remark indicates a rom code suffix
m pd78363a, 78365a, 78366a, 78368a 4 p00-p07 : port0 p10-p17 : port1 p20-p25 : port2 p30-p36 : port3 p40-p47 : port4 p50-p57 : port5 p70-p77 : port7 p80-p85 : port8 p90-p93 : port9 rtp0-rtp3 : real-time port nmi : nonmaskable interrupt intp0-intp4 : interrupt from peripherals to00-to05, to04 : timer output ti : timer input tiud : timer input up down counter tcud : timer control up down counter tclrud : timer clear up down counter ani0-ani7 : analog input t x d0, t x d1 : transmit data r x d0, r x d1 : receive data si : serial input so : serial output sb0, sb1 : serial bus sck : serial clock pwm0, pwm1 : pulse width modulation output wdto : watchdog timer ouput mode0, mode1 : mode ad0-ad7 : address/data bus a8-a15 : address bus astb : address strobe rd : read strobe wr : write strobe reset : reset x1, x2 : crystal av dd : analog v dd av ss : analog v ss av ref : analog reference voltage v dd : power supply v ss : ground ic : internally connected
m pd78363a, 78365a, 78366a, 78368a 5 125 ns (internal clock: 16 mhz, external clock: 8 mhz) 24k bytes none 32k bytes 48k bytes 768 bytes 2k bytes 64k bytes (externally expandable) 8 bits 16 8 banks 115 ? 16-bit transfer/operation ? multiplication/division (16 bits 16 bits, 32 bits ? 16 bits) ? bit manipulation ? string ? sum-of-products operation (16 bits 16 bits + 32 bits) ? relative operation 14 (of which 8 are shared with analog input) 49 31 49 ? 16-bit timer 1 10-bit dead time timer 3 16-bit compare register 4 2 kinds of output mode can be selected mode 0, set-reset output: 6 channels mode 1, buffer output: 6 channels ? 16-bit timer 1 16-bit compare register 1 ? 16-bit timer 1 16-bit capture register 1 16-bit capture/compare register 1 ? 16-bit timer 1 16-bit capture register 2 16-bit capture/compare register 1 ? 16-bit timer 1 16-bit compare register 2 16-bit resolution pwm output: 1 channel pulse outputs associated with real-time pulse unit: 4 lines 8-/9-/10-/12-bit resolution variable pwm output: 2 channels 10-bit resolution, 8 channels dedicated baud rate generator uart (w/pin selection function): 1 channel clocked serial interface/sbi: 1 channel ? external: 6, internal: 14 (of which 2 are multiplexed with external) ? 4 priority levels can be specified through software ? 3 types of interrupt processing modes selectable (vectored interrupt, macro service, and context switching) 80-pin plastic qfp (14 20 mm) ? watchdog timer ? standby function (halt and stop modes) functional outline minimum instruction execution time internal memory rom ram memory space general-purpose registers number of basic instructions instruction set i/o lines input i/o real-time pulse unit real-time output port pwm unit a/d converter serial interface interrupt function package others product name item m pd78363a m pd78365a m pd78366a m pd78368a
m pd78363a, 78365a, 78366a, 78368a 6 49 can be set in input or output mode in units of 8 bits. in external memory expansion mode, this port functions as multiplexed address/data bus (ad0-ad7). can be set in input or output mode in 1-bit units. in external memory expansion mode, this port functions as address bus (a8-a15). can be set in input or output mode in 1-bit units. in external memory expansion mode, p90 outputs rd strobe signal, and p91 outputs wr strobe signal. sets port 4 in input or output mode in units of 8 bits. in external memory expansion mode, sets memory expansion width of ports 4 and 5. sets port 5 in input or output mode in 1-bit units. ? in ordinary operation mode: mode0, 1 = ll ? in rom-less mode: mode0, 1 = hh differences between m pd78363a, 78365a, 78366a, and 78368a rom internal rom ram input i/o lines i/o port 4 (p40-p47) port 5 (p50-p57) port 9 (p90-p93) memory expansion mode register (mm) port 5 mode register (pm5) setting of mode0, mode1 product name item 24k bytes 32k bytes 48k bytes none 786 bytes 2k bytes 14 (of which 8 are multiplexed with analog input) 31 always functions as multiplexed address/ data bus (ad0-ad7). always functions as address bus (a8-a15) p90 always functions as rd strobe signal output pin, and p91 always functions as wr strobe signal output pin. p92 and p93 function as i/o port lines. always fixed to external memory expansion mode. none ? always set as follows: mode0, 1 = hh m pd78363a m pd78366a m pd78365a m pd78368a
m pd78363a, 78365a, 78366a, 78368a 7 block diagram p0 p1 p2 p3 p4 p5 p6 p7 p8 8 8 6 7 8 8 8 6 4 v dd v ss wdto pwm av dd av ss av ref intp2 ani to ti tiud tclrud tcud sck so/sb0 si/b1 r x d t x d rtp nmi intp 5 5 4 2 2 4 2 4 2 exu rom/ram bcu x1 x2 reset astb rd wr mode1 mode0 a8-a15 ad0-ad7 programmable interrupt controller timer/counter unit (real-time pulse unit) serial interface (sbi) (uart) real-time output port general registers 128 8 & data memory 128 8 main ram micro sequence control micro rom a/d converter rwm watchdog timer port alu rom 24k 8 32k 8 48k 8 & peripheral ram 512 8 1792 8 system control & bus control & prefetch control 8 8 8 7 remark the internal rom and ram capacities differ depending on the product.
m pd78363a, 78365a, 78366a, 78368a 8 contents 1. pin functions ............................................................................................................................... .... 10 1.1 port pins ............................................................................................................................... ...... 10 1.2 pins other than port pins .................................................................................................. 11 1.3 pin i/o circuits and processing of unused pins ....................................................... 13 2. cpu architecture ............................................................................................................ 15 2.1 memory space ........................................................................................................................... 15 2.2 data memory addressing .................................................................................................... 18 2.3 processor registers ........................................................................................................... 20 2.3.1 control registers ......................................................................................................... ........ 21 2.3.2 general-purpose registers ................................................................................................. .22 2.3.3 special function registers (sfr) ........................................................................................23 3. functional blocks ........................................................................................................... 29 3.1 execution unit (exu) ............................................................................................................... 29 3.2 bus control unit (bcu) ......................................................................................................... 29 3.3 rom/ram ............................................................................................................................... ........ 29 3.4 port functions ........................................................................................................................ 30 3.5 clock generator circuit ................................................................................................... 32 3.6 real-time pulse unit (rpu) .................................................................................................. 34 3.7 real-time output port (rtp) .............................................................................................. 42 3.8 a/d converter .......................................................................................................................... 43 3.9 serial interface ..................................................................................................................... 44 3.10 pwm unit ............................................................................................................................... ....... 46 3.11 watchdog timer (wdt) .......................................................................................................... 47 4. interrupt functions ................................................................................................................... 48 4.1 outline ............................................................................................................................... .......... 48 4.2 macro service .......................................................................................................................... 49 4.3 context switching ................................................................................................................. 52 4.3.1 context switching function by interrupt request ................................................................ 52 4.3.2 context switching function by brkcs instruction ..............................................................53 4.3.3 restoration from context switching .....................................................................................53 5. external device expansion function ............................................................................. 54 6. standby functions ...................................................................................................................... 55 7. reset function ............................................................................................................................... 56 8. instruction set .............................................................................................................................. 5 7 9. example of system configuration ........................................................................... 71 10. electrical specifications ............................................................................................ 72
m pd78363a, 78365a, 78366a, 78368a 9 11. package drawing .............................................................................................................. 83 12. recommended soldering conditions ...................................................................... 84 appendix a. differences between m pd78366a and m pd78328 ................................... 85 appendix b. tools ..................................................................................................................... 86 b.1 development tools ............................................................................................................... 86 b.2 embedded software .............................................................................................................. 91
m pd78363a, 78365a, 78366a, 78368a 10 p00-p03 p04 p05 p06 p07 p10-p17 p20 p21 p22 p23 p24 p25 p30 p31 p32 p33 p34 p35 p36 p40-p47 p50-p57 p70-p77 p80-p85 p90 p91 p92 p93 rtp0-rtp3 pwm0 tcud/pwm1 tiud/to40 tclrud C nmi intp0 intp1 intp2 intp3/ti intp4 t x d0 r x d0 so/sb0 si/sb1 sck t x d1 r x d1 ad0-ad7 a8-a15 ani0-ani7 to00-to05 rd wr C C i/o i/o input i/o i/o i/o input i/o i/o pin name i/o function shared by: port 0. 8-bit i/o port. can be set in input or output mode in 1-bit units. port 1. 8-bit i/o port. can be set in input or output mode in 1-bit units. port 2. 6-bit input port. port 3. 7-bit i/o port. can be set in input or output mode in 1-bit units. port 4. 8-bit i/o port. can be set in input or output mode in 8-bit units. port 5. 8-bit i/o port. can be set in input or output mode in 1-bit units. port 7. 8-bit input port port 8. 6-bit i/o port. can be set in input or output mode in 1-bit units. port 9. 4-bit i/o port. can be set in input or output mode in 1-bit units. 1. pin functions 1.1 port pins
m pd78363a, 78365a, 78366a, 78368a 11 p00-p03 p20 p21 p22 p23 p24/ti p25 p24/intp3 p05/pwm1 p06/to40 p07 p80-p85 p06/tiud p70-p77 p30 p35 p31 p36 p34 p33/sb1 p32/sb0 p32/so p33/si p04 p05/tcud C p40-p47 p50-p57 C p90 p91 rtp0-rtp3 nmi intp0 intp1 intp2 intp3 intp4 ti tcud tiud tclrud to00-to05 to40 ani0-ani7 t x d0 t x d1 r x d0 r x d1 sck si so sb0 sb1 pwm0 pwm1 wdto ad0-ad7 a8-a15 astb rd wr real-time output port that outputs pulses in synchronization with trigger signal from real-time pulse unit. non-maskable interrupt request input. external interrupt request input. external count clock input to timer 1. count operation selection control signal input to up/down counter (timer 4). external count clock input to up/down counter (timer 4). clear signal input to up/down counter (timer 4). pulse output from real-time pulse unit. analog input to a/d converter. serial data output of asynchronous serial interface. serial data input of asynchronous serial interface. serial clock input/output of clocked serial interface. serial data input of clocked serial interface in 3-line mode. serial data output of clocked serial interface in 3-line mode. serial data input/output of clocked serial interface in sbi mode. pwm signal output. signal output indicating overflow of watchdog timer (generates non- maskable interrupt). multiplexed address/data bus when memory is externally expanded. address bus when memory is externally expanded. outputs timing signal at which address information output from ad0-ad7 and a8-a15 pins to access external memory is to be latched. read strobe signal output to external memory. write strobe signal output to external memory. output input input output input output input i/o input ouput i/o output output i/o output pin name i/o function shared by: 1.2 pins other than port pins (1/2)
m pd78363a, 78365a, 78366a, 78368a 12 pin name i/o function shared by: mode0 mode1 reset x1 x2 av ref av dd av ss v dd v ss ic C C C C C C C C C control signal input to set operation mode. with m pd78363a, 78366a, and 78368a mode0 and mode1 are usually connected to v ss . with m pd78365a, mode0 and mode1 are always connected to v dd . system reset input crystal oscillator connecting pins for system clock. if a clock is externally supplied, input it to pin x1. leave pin x2 open. a/d converter reference voltage input. a/d converter analog power supply. a/d converter gnd. positive power supply gnd internally connected. connect this pin to v ss . input input input C input C C C C C 1.2 pins other than port pins (2/2)
m pd78363a, 78365a, 78366a, 78368a 13 1.3 pin i/o circuits and processing of unused pins table 1-1 shows the i/o circuit types of the respective pins, and recommended connections of the unused pins. figure 1-1 shows the circuits of the respective pins. table 1-1. pin i/o circuit type and recommended connections of unused pins pin i/o circuit type recommended connections p00/rtp0-p03/rtp3 p04/pwm0 p05/tcud/pwm1 p06/tiud/to40 p07/tclrud p10-p17 p20/nmi p21/intp0 p22/intp1 p23/intp2 p24/intp3/ti p25/intp4 p30/t x d0 p31/r x d0 p32/so/sb0 p33/si/sb1 p34/sck p35/t x d1 p36/r x d1 p40/ad0-p47/ad7 p50/a8-p57/a15 p70/ani0-p77/ani7 p80/to00-p85/to05 p90/rd p91/wr p92, p93 astb wdto mode0, mode1 reset av ref , av ss av dd ic 5-a 2 2-a 5-a 8-a 5-a 9 5-a 5 19 1 2 C input : independently connect to v dd or v ss through resistor output : leave unconnected connect to v ss input : independently connect to v dd or v ss through resistor output : leave unconnected connect to v ss input : independently connect to v dd or v ss through resistor output : leave unconnected connect to v ss C connect to v ss connect to v dd connect to v ss
m pd78363a, 78365a, 78366a, 78368a 14 figure 1-1. pin i/o circuits type 1 type 5-a type 2 type 8-a type 2-a schmitt trigger input with hysteresis characteristics type 9 type 19 type 5 schmitt trigger input with hysteresis characteristics v dd p-ch n-ch in in v dd p-ch in pull-up enable data output disable intput enable n-ch p-ch v dd in/out pull-up enable data output disable input enable v dd p-ch in/out v dd p-ch n-ch v dd p-ch in/out v dd p-ch n-ch pull-up enable data output disable p-ch n-ch in + v ref input enable n-ch out comparator (threshold voltage)
m pd78363a, 78365a, 78366a, 78368a 15 2. cpu architecture 2.1 memory space the m pd78366a can access a memory space of 64k bytes. figures 2-1 through 2-3 show the memory map. figure 2-1. memory map ( m pd78368a) memory space (64 k 8) data memory program memory data memory program memory data memory feffh ffffh ff00h fdffh ff00h f6ffh f700h 0000h special function register (sfr) (256 8) main ram (256 8) external memory note (14080 8) internal rom (49152 8) feffh fe80h fe25h fe06h f700h bfffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h program area program area callt instruction table area (64 8) vector table area (64 8) general-purpose register (128 8) mode0, 1 = hh rom-less mode mode0, 1 = ll macro service control (32 8) data area (768 8) external memory (63232 8) 0fffh 0000h bfffh c000h callf instruction entry area (2048 8) peripheral ram (1792 8) note accessed in external memory expansion mode. caution for word access (including stack operations) to the main ram area (fe00h-feffh), the address that specifies the operand must be an even value.
m pd78363a, 78365a, 78366a, 78368a 16 figure 2-2. memory map ( m pd78365a, 78366a) memory space (64 k 8) data memory program memory data memory program memory data memory feffh ffffh ff00h fdffh ff00h f6ffh f700h 0000h special function register (sfr) (256 8) main ram (256 8) external memory note (30464 8) internal rom (32768 8) feffh fe80h fe25h fe06h f700h 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h program area program area callt instruction table area (64 8) vector table area (64 8) general-purpose register (128 8) mode0, 1 = hh pd78365a pd78366a in orm-less mode m m m mode0, 1 = ll ( pd78366a) macro service control (32 8) data area (2048 8) external memory (63232 8) 0fffh 0000h 7fffh 8000h callf instruction entry area (2048 8) peripheral ram (1792 8) note accessed in external memory expansion mode. caution for word access (including stack operations) to the main ram area (fe00h-feffh), the address that specifies the operand must be an even value.
m pd78363a, 78365a, 78366a, 78368a 17 figure 2-3. memory map ( m pd78363a) memory space (64 k 8) data memory program memory data memory program memory data memory feffh ffffh ff00h fdffh ff00h fbffh fc00h 0000h special function register (sfr) (256 8) main ram (256 8) external memory note (39936 8) internal rom (24576 8) feffh fe80h fe25h fe06h fc00h 5fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h program area program area callt instruction table area (64 8) vector table area (64 8) general-purpose register (128 8) mode0, 1 = hh rom-less mode mode0, 1 = ll macro service control (32 8) data area (768 8) external memory (64512 8) 0fffh 0000h 5fffh 6000h callf instruction entry area (2048 8) peripheral ram (512 8) note accessed in external memory expansion mode. caution for word access (including stack operations) to the main ram area (fe00h-feffh), the address that specifies the operand must be an even value.
m pd78363a, 78365a, 78366a, 78368a 18 2.2 data memory addressing the m pd78366a is provided with many addressing modes that improve the operability of the memory and can be used with high-level languages. especially, an area of addresses f700h-ffffh (in the m pd78363a, fc00h-ffffh) to which the data memory is mapped can be addressed in a mode peculiar to the functions provided in this area, including special function registers (sfr) and general-purpose registers. figure 2-4. data memory addressing ( m pd78368a) ffffh ff20h ff1fh fe20h fe1fh f700h f6ffh ff00h feffh fe80h fe7fh fe00h fdffh 6c00h bfffh 0000h special function register (sfr) general-purpose register main ram peripheral ram internal rom note external memory sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing based indexed addressing (with displacement) note is external memory in the romless mode. caution for word access (including stack oprations) to the main ram area (fe00h-feffh), the address that specifies the operand must be an even value.
m pd78363a, 78365a, 78366a, 78368a 19 figure 2-5. data memory addressing ( m pd78365a, 78366a) ffffh ff20h ff1fh fe20h fe1fh f700h f6ffh ff00h feffh fe80h fe7fh fe00h fdffh 8000h 7fffh 0000h special function register (sfr) general-purpose register main ram peripheral ram internal rom note external memory sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing based indexed addressing (with displacement) note is external memory in the romless mode of the m pd78365a or m pd78366a. caution for word access (including stack oprations) to the main ram area (fe00h-feffh), the address that specifies the operand must be an even value.
m pd78363a, 78365a, 78366a, 78368a 20 figure 2-6. data memory addressing ( m pd78363a) ffffh ff20h ff1fh fe20h fe1fh fc00h fbffh ff00h feffh fe80h fe7fh fe00h fdffh 6000h 5fffh 0000h special function register (sfr) general-purpose register main ram peripheral ram internal rom note external memory sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing based indexed addressing (with displacement) note is external memory in the romless mode. caution for word access (including stack oprations) to the main ram area (fe00h-feffh), the address that specifies the operand must be an even value. 2.3 processor registers the m pd78366a is provided with the following three types of processor registers: ? control registers ? general-purpose registers ? special function registers (sfrs)
m pd78363a, 78365a, 78366a, 78368a 21 2.3.1 control registers (1) program counter (pc) this is a 16-bit register that holds an address of the instruction to be executed next. (2) program status word (psw) this 16-bit register indicates the status of the cpu as a result of instruction execution. (3) stack pointer (sp) this 16-bit register indicates the first address of the stack area (lifo) of the memory. (4) cpu control word (ccw) this 8-bit register is used to control the cpu. figure 2-7. configuration of control registers pc psw sp ccw 7 0 15 0 tpf : table position flag ccw 000000tpf0 7 0 figure 2-8. configuration of psw psw uf rbs2 rbs1 rbs0 0 0 0 0 15 8 s z rss ac ie p/v 0 cy 7 0 uf : user flag rbs0-rbs2: register bank select flag s : sign flag (msb of execution result) z : zero flag rss : register set select flag ac : auxiliary carry flag ie : interrupt request enable flag p/v : parity/overflow flag cy : carry flag figure 2-9. configuration of ccw
m pd78363a, 78365a, 78366a, 78368a 22 2.3.2 general-purpose registers the m pd78366a is provided with eight banks of general-purpose registers with one bank consisting of 8 words 16 bits. figure 2-10 shows the configuration of the general-purpose register banks. the general- purpose registers are mapped to an area of addresses fe80h-feffh. each of these registers can be used as an 8-bit register. in addition, two registers can be used as one 16-bit register pair (refer to figure 2-11 ). these general-purpose registers facilitate complicated multitask processing. figure 2-10. configuration of general-purpose register banks 15 0 rp0 rp1 rp2 rp3 rp4 rp5 rp6 rp7 bank 7 bank 1 bank 0 figure 2-11. processing bits of general-purpose registers rbnk0 rbnk1 rbnk2 rbnk3 rbnk4 rbnk5 rbnk7 rbnk6 r15 r13 r11 r9 r7 r5 r3 r1 r14 r12 r10 r8 r6 r4 r2 r0 rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 (fh) (dh) (bh) (9h) (7h) (5h) (3h) (1h) (eh) (ch) (ah) (8h) (6h) (4h) (2h) (0h) feffh fe80h 8-bit processing 16-bit processing 7 07 0 15 0
m pd78363a, 78365a, 78366a, 78368a 23 2.3.3 special function registers (sfr) special function registers (sfrs) are registers assigned special functions such as mode registers and control registers for internal peripheral hardware, and are mapped to a 256-byte address space at ff00h through ffffh. table 2-1 lists the sfrs. the meanings of the symbols in this table are as follows: ? symbol ................................... indicates the mnemonic symbol for an sfr. this mnemonic can be coded in the operand field of an instruction. ? r/w ........................................ indicates whether the sfr can be read or written. r/w : read/write r : read only w : write only ? bit units for manipulation ...... indicates bit units in which the sfr can be manipulated. the sfrs that can be manipulated in 16-bit units can be coded as an sfrp operand. specify an even address for these sfrs. the sfrs that can be manipulated in 1-bit units can be coded as the operand of bit manipulation instructions. ? on reset ................................. indicates the status of the register at reset input. cautions 1. do not access the addresses in the range ff00h through ffffh to which no special function register is allocated. if these addresses are accessed, malfunctioning may occur. 2. do not write data to the read-only registers. otherwise, the internal circuit may not operate normally. 3. when using read data as byte data, process undefined bit(s) first. 4. tout and txs are write-only registers. do no read these registers. 5. bits 0, 1, and 4 of sbic are write-only bits. when these bits are read, they are always "0".
m pd78363a, 78365a, 78366a, 78368a 24 table 2-1. list of special function registers (1/5) bit units for manipulation 1 bit 8 bits 16 bits on reset address special function register (sfr) symbol r/w undefined ff00h ff01h ff02h ff03h ff04h ff05h ff07h ff08h ff09h ff10h ff11h ff12h ff13h ff14h ff15h ff16h ff17h ff18h ff19h ff1ah ff1bh ff1ch ff1dh ff1eh ff1fh ff20h ff21h ff23h ff25h ff28h ff29h ff2ch ff2dh ff2eh ff2fh ff30h ff31h ff32h ff33h port 0 port 1 port 2 port 3 port 4 port 5 port 7 port 8 port 9 compare register 00 compare register 01 compare register 02 compare register 03 buffer register cm00 buffer register cm01 buffer register cm02 timer register 0 port 0 mode register port 1 mode register port 3 mode register port 5 mode register port 8 mode register port 9 mode register reload register timer unit mode register 0 timer unit mode register 1 compare register 10 timer register 1 r/w r r/w r r/w r r/w r/w r l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C CC l l CC l l CC l l CC l l CC l l CC l l CC l l CC l l l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C CC l l l l l l C l l l l C CC l l CC l l 0000h ffh 111 1111b ffh 11 1111b 1111b undefined 00h undefined 0000h p0 p1 p2 p3 p4 note p5 note p7 p8 p9 cm00 cm01 cm02 cm03 bfcm00 bfcm01 bfcm02 tm0 pm0 pm1 pm3 pm5 note pm8 pm9 dtime tum0 tum1 cm10 tm1 note not provided for the m pd78365a.
m pd78363a, 78365a, 78366a, 78368a 25 table 2-1. list of special function registers (2/5) bit units for manipulation 1 bit 8 bits 16 bits on reset address special function register (sfr) symbol r/w ff34h ff35h ff36h ff37h ff38h ff39h ff3ah ff3bh ff3ch ff3dh ff40h ff43h ff44h ff45h ff48h ff4eh ff4fh ff50h ff51h ff52h ff53h ff54h ff55h ff56h ff57h ff58h ff59h ff5ah ff5bh ff5ch ff5dh ff5eh ff5fh ff60h ff61h ff62h ff68h capture/compare register 20 capture register 20 timer register 2 buffer register cm03 external interrupt mode register 0 external interrupt mode register 1 port 0 mode control register port 3 mode control register pull-up resistor option register l pull-up resistor option register h port 8 mode control register sampling control register 0 sampling control register 1 capture/compare register 30 capture register 30 capture register 31 timer register 3 compare register 40 compare register 41 timer register 4 timer control register 4 timer out register real-time output port register real-time output port mode register port read control register a/d converter mode register cc20 ct20 tm2 bfcm03 intm0 intm1 pmc0 pmc3 puol puoh pmc8 smpc0 smpc1 cc30 ct30 ct31 tm3 cm40 cm41 tm4 tmc4 tout rtp rtpm prdc adm CC l l CC l l CC l l CC l l l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C CC l l CC l l CC l l CC l l CC l l CC l l CC l l C l l C C l l C l l l l C l l l l C l l l l C l l l l C r/w r r/w r r/w r r/w w r/w undefined 0000h underfined 00h 000 0000b 00h 00 0000b 00h undefined 0000h undefined 0000h 00h 01 0101b undefined 00h
m pd78363a, 78365a, 78366a, 78368a 26 table 2-1. list of special function registers (3/5) bit units for manipulation 1 bit 8 bits 16 bits on reset address special function register (sfr) symbol r/w ff70h ff71h ff72h ff73h ff74h ff75h ff76h ff77h ff78h ff79h ff7ah ff7bh ff7ch ff7dh ff7eh ff7fh ff80h ff82h ff84h ff85h ff86h ff88h ff8ah ff8ch ff8eh ffa0h ffa1h ffa2h ffa2h ffa3h slave buffer register 0 slave buffer register 1 slave buffer register 2 slave buffer register 3 slave buffer register 4 slave buffer register 5 master buffer register 0 master buffer register 1 master buffer register 2 master buffer register 3 master buffer register 4 master buffer register 5 timer control register 0 timer control register 1 timer control register 2 timer control register 3 clocked serial interface mode register serial bus interface control register baud rate generator control register baud rate generator compare register serial i/o shift register asynchronous serial interface mode register asynchronous serial interface status register serial receive buffer: uart serial transfer shift register: uart pwm control register 0 pwm control register 1 pwm register 0l pwm register 0 sbuf0 sbuf1 sbuf2 sbuf3 sbuf4 sbuf5 mbuf0 mbuf1 mbuf2 mbuf3 mbuf4 mbuf5 tmc0 tmc1 tmc2 tmc3 csim sbic brgc brg sio asim asis rxb txs pwmc0 pwmc1 pwm0l pwm0 l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C C l l C l l l l C l l l l C l l l l C C l l C C l l C l l l l C l l l l C l l l l C CC l l undefined 00h undefined 80h 00h undefined 00h undefined note bits 7 and 5 : read/write bits 6, 3, and 2 : read-only bits 4, 1, and 0 : write-only r/w r/w note r/w r w r/w
m pd78363a, 78365a, 78366a, 78368a 27 table 2-1. list of special function registers (4/5) bit units for manipulation 1 bit 8 bits 16 bits on reset address special function register (sfr) symbol r/w l l l l C CC l l l l l l C l l l l C l l l l C CC l l l l l l C CC l l C l l C CC l l C l l C CC l l C l l C CC l l C l l C CC l l C l l C CC l l C l l C CC l l C l l C CC l l C l l C C l l C l l l l C C l l C pwm1l pwm1 ispr imc mk0l mk0 mk0h adcr0 adcr0h adcr1 adcr1h adcr2 adcr2h adcr3 adcr3h adcr4 adcr4h adcr5 adcr5h adcr6 adcr6h adcr7 adcr7h stbc note ccw wdm note r/w r r/w r r/w undefined 00h 80h ffh ffffh ffh undefined 0000 000b 00h ffa4h ffa4h ffa5h ffa8h ffaah ffach ffach ffadh ffadh ffb0h ffb1h ffb1h ffb2h ffb3h ffb3h ffb4h ffb5h ffb5h ffb6h ffb7h ffb7h ffb8h ffb9h ffb9h ffbah ffbbh ffbbh ffbch ffbdh ffbdh ffbeh ffbfh ffbfh ffc0h ffc1h ffc2h pwm register 1l pwm register 1 in-service priority register interrupt mode control register interrupt mask register 0l interrupt mask register 0 interrupt mask register 0h a/d conversion result register 0 a/d conversion result register 0h a/d conversion result register 1 a/d conversion result register 1h a/d conversion result register 2 a/d conversion result register 2h a/d conversion result register 3 a/d conversion result register 3h a/d conversion result register 4 a/d conversion result register 4h a/d conversion result register 5 a/d conversion result register 5h a/d conversion result register 6 a/d conversion result register 6h a/d conversion result register 7 a/d conversion result register 7h standby control register cpu control word watchdog timer mode register note can be written when a special instruction is executed.
m pd78363a, 78365a, 78366a, 78368a 28 table 2-1. list of special function registers (5/5) bit units for manipulation 1 bit 8 bits 16 bits on reset address special function register (sfr) symbol r/w note c0aah undefined 43h memory expansion mode register programmable wait control register external sfr area interrupt control register (intov3) interrupt control register (intp0/intcc30) interrupt control register (intp1) interrupt control register (intp2) interrupt control register (intp3/intcc20) interrupt control register (intp4) interrupt control register (inttm0) interrupt control register (intcm03) interrupt control register (intcm10) interrupt control register (intcm40) interrupt control register (intcm41) interrupt control register (intser) interrupt control register (intsr) interrupt control register (intst) interrupt control register (intcsi) interrupt control register (intad) ffc4h ffc6h ffc7h ffd0h | ffdfh ffe0h ffe1h ffe2h ffe3h ffe4h ffe5h ffe6h ffe7h ffe8h ffe9h ffeah ffebh ffech ffedh ffeeh ffefh mm pwc C ovic3 pic0 pic1 pic2 pic3 pic4 tmic0 cmic03 cmic10 cmic40 cmic41 seric sric stic csiic adic l l l l C CC l l l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C l l l l C note the value of the mw register at reset time differs depending on the product. m pd78363a : 60h m pd78365a, 78366a : 20h m pd78368a : 00h r/w
m pd78363a, 78365a, 78366a, 78368a 29 3. functional blocks 3.1 execution unit (exu) exu controls address computation, arithmetic and logical operations, and data transfer through microprogram. exu has an internal main ram. this ram can be accessed by instructions faster than the peripheral ram. 3.2 bus control unit (bcu) bcu starts necessary bus cycles according to the physical address obtained by the execution unit (exu).if exu does not request start of the bus cycle, an address is generated to prefetch an instruction. the prefetched op code is stored in an instruction queue. 3.3 rom/ram the internal rom and ram capacities differ depending on the product. the m pd78363a has a 24-kb rom and a 512-b peripheral ram. the m pd78366a has a 32-kb rom and a 1792-b peripheral ram. the m pd78368a has a 48-kb rom and a 1792-b peripheral ram. the m pd78365a does not have a rom and only has a 1792-b peripheral ram. access to the rom can be disabled by using the mode0 and mode1 pins, in which case an external memory of 64 kb can be accessed.
m pd78363a, 78365a, 78366a, 78368a 30 3.4 port functions the m pd78366a is provided with the ports shown in figure 3-1 for various control operations. the functions of each port are listed in table 3-1. these ports function not only as digital ports but also as input/output lines of the internal hardware. figure 3-1. port configuration p00 p07 p10 p17 p20 p25 p30 p36 8 8 p50 p57 p70-p77 p80 p85 p90 p93 p40-p47 port 0 port 1 port 2 port 3 port 4 port 5 port 8 port 7 port 9
m pd78363a, 78365a, 78366a, 78368a 31 table 3-1. functions of each port 8-bit i/o port. can be set in input or output mode in 1-bit units. 8-bit i/o port. can be set in input or output mode in 1-bit units. 6-bit input port. 7-bit i/o port. can be set in input or output in 1-bit units. 8-bit i/o port. can be set in input or output mode in 8-bit units. 8-bit i/o port. can be set in input or output mode in 1-bit units. 8-bit input port. 6-bit i/o port. can be set in input or output mode in 1-bit units. 4-bit i/o port. can be set in input or output mode in 1-bit units. in control mode, serves as real-time output port (rtp), or input operation control signal of real-time pulse unit (rpu) and output pwm signal. inputs external interrupt and count pulse of real-time pulse unit (rpu) (fixed to the control mode). in control mode, inputs/outputs signals of serial interfaces (uart, csi). address data bus (ad0-ad7) when memory is externally expanded. address bus (a8-a15) when memory is externally expanded. input analog signals to a/d converter (fixed to the control mode). in control mode, outputs timer of real-time pulse unit (rpu). outputs control signal when memory is externally expanded. port port function multiplexed function port 0 port 1 port 2 port 3 port 4 port 5 port 7 port 8 port 9
m pd78363a, 78365a, 78366a, 78368a 32 3.5 clock generator circuit the clock generator circuit generates and controls the internal system clock (clk) that is supplied to the cpu. figure 3-2. block diagram of clock generator circuit x1 x2 f xx or f x f clk 1/2 system cloock oscillator circuit internal system clock (clk) stop mode frequency divider 1/2 pll control circuit frequency divider remarks 1. f xx : crystal oscillation frequency 2. f x : external clock frequency 3. f clk : internal system clock frequency by connecting an 8-mhz crystal resonator across the x1 and x2 pins, an internal system clock of up to 16 mhz (f clk ) can be generated. the system clock oscillation circuit oscillates by using the crystal resonator connected across the x1 and x2 pins. it stops oscillation in standby mode. an external clock can also be input. to do so, input the clock signal to the x1 pin and leave the x2 pin open. caution do not set stop mode when the external clock is used.
m pd78363a, 78365a, 78366a, 78368a 33 figure 3-3. external circuit of system clock oscillator circuit (a) crystal oscillator (b) external clock pd78366a m v ss x1 x2 pd78366a m x1 x2 open cautions 1. wire the portion enclosed by dotted line in figure 3-3 as follows to avoid adverse influences due to wiring capacity when using the system clock oscillation circuit. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal line. make sure that the wiring is not close to lines through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as v ss . do not ground the circuit to a ground pattern through which a high current flows. ? do not extract signals from the oscillator circuit. 2. to input an external clock, do not connect a load such as wiring capacitance to the x2 pin.
m pd78363a, 78365a, 78366a, 78368a 34 3.6 real-time pulse unit (rpu) the real-time pulse unit (rpu) can measure pulse intervals and frequencies, and output programmable pulses (six channels of pwm control signals). the rpu consists of five 16-bit timers (timers 0 through 4), of which one is provided with a 10-bit dead time timer, which is ideal for inverter control. in addition, a function to turn off the output by the software or an external interrupt is also provided. each timer has the following features: ? timer 0 : controls the pwm period of the to00 through to05 pins. in addition, operates as a general-purpose interval timer. timer 0 has the following five operation modes: ? general-purpose interval timer mode ? pwm mode 0 (symmetrical triangular wave) ? pwm mode 0 (asymmetrical triangular wave) ? pwm mode 0 (saw-tooth wave) ? pwm mode 1 ? timer 1 : operates as a general-purpose interval timer. ? timers 2, 3 : has a programmable input sampling circuit that rejects the noise of an input signal, and a capture function. ? timer 4 : operates as a general-purpose timer or an up-down counter. when operating as a general- purpose timer, controls the pwm cycle of the to40 output pin. timer 4 has the following two operation modes: ? general-purpose timer mode ? up/down counter mode (udc mode)
m pd78363a, 78365a, 78366a, 78368a 35 the rpu consists of the hardware shown in table 3-2. figures 3-4 through 3-12 show the block diagrams of the respective timers. table 3-2. configuration of real-time pulse unit (rpu) 16-bit compare register (cm00) C 16-bit compare register (cm01) C 16-bit compare register (cm02) C 16-bit compare register (cm03) intcm03 16-bit compare register (cm10) intcm10 16-bit capture/compare register (cc20) intcc20 16-bit capture register (ct20) C 16-bit capture/compare register (cc30) intcc30 16-bit capture register (ct30) C 16-bit capture register (ct31) C 16-bit compare register (cm40) intcm40 16-bit compare register (cm41) intcm41 timer 0 16-bit timer (tm0) timer 1 16-bit timer (tm1) timer 2 16-bit timer (tm2) timer 3 16-bit timer (tm3) timer 4 16-bit timer (tm4) compare register coincidence interrupt capture trigger timer output timer clear C 6 intcm03 C C intcm10 intp3 C intcc20 intp0 intp1 C intcc30 intp4 tclrud intcm40 C1 timer register register
m pd78363a, 78365a, 78366a, 78368a 36 figure 3-4. block diagram of timer 0 (pwm mode 0 ... symmetrical triangular wave, asymmetrical triangular wave) bfcm03 cm03 tm0 bfcm00 cm00 r s dtm0 r s to00 (u phase) underflow r s to01 (u phase) bfcm01 cm01 r s dtm1 r s to02 (v phase) underflow r s to03 (v phase) bfcm02 cm02 r s dtm2 r s to04 (w phase) underflow r s to05 (w phase) intcm03 inttm0 16 16 f clk f clk /2 f clk /4 f clk /8 f clk /16 u/d up = 0 down = 1 dtime f clk 10 alvto output off function by external interrupt and software tm0 : timer register alvto: bit 2 of tum0 register cm00-cm03 : compare registers u/d : bit 3 of tmc0 register bfcm00-bfcm03: buffer registers dtime : reload register dtm0-dtm2 : dead time timers remark f clk : internal system clock
m pd78363a, 78365a, 78366a, 78368a 37 figure 3-5. block diagram of timer 0 (pwm mode 0 ... saw-tooth wave) bfcm03 cm03 tm0 bfcm00 cm00 r s dtm0 r s to00 (u phase) underflow r s to01 (u phase) bfcm01 cm01 r s dtm1 r s to02 (v phase) underflow r s to03 (v phase) bfcm02 cm02 r s dtm2 r s to04 (w phase) underflow r s to05 (w phase) intcm03 16 16 f clk f clk /2 f clk /4 f clk /8 f clk /16 dtime f clk 10 alvto output off function by external interrupt and software clear tm0 : timer register cm00-cm03 : compare registers bfcm00-bfcm03: buffer registers dtime : reload register dtm0-dtm2 : dead time timers alvto : bit 2 of tum0 register remark f clk : internal system clock
m pd78363a, 78365a, 78366a, 78368a 38 figure 3-6. block diagram of timer 0 (pwm mode 1) mbuf1 mbuf0 mbuf3 mbuf2 mbuf5 mbuf4 bfcm03 cm03 tm0 bfcm00 cm00 bfcm01 cm01 bfcm02 cm02 intcm03 16 16 f clk f clk /2 f clk /4 f clk /8 f clk /16 clear dtm0 dtime t dtm1 t dtm2 t 10 f clk underflow underflow underflow sbuf1 sbuf0 sbuf3 sbuf2 sbuf5 sbuf4 6-bit buffer register 6-bit buffer register 6-bit write-only register tout output off function by external interrupt and software to00 (u phase) to02 (v phase) to04 (w phase) to01 (u phase) to03 (v phase) to05 (w phase) tm0 : timer register mbuf0-mbuf5 : master buffer registers cm00-cm03 : compare registers sbuf0-sbuf5 : slave buffer registers bfcm00-bfcm03: buffer registers tout : timer out register dtime : reload register dtm0-dtm2 : dead time timers remark f clk : internal system clock
m pd78363a, 78365a, 78366a, 78368a 39 figure 3-7. block diagram of timer 0 (general-purpose interval timer mode) compare register cm03 timer register tm0 16 master buffer register (mbuf0) slave buffer register (sbuf0) timer out register (tout) 6 6 intcm03 clear output off function by external interrupt and software to00 to02 to04 to01 to03 to05 figure 3-8. block diagram of timer 1 f clk /4 f clk /8 f clk /16 ti intcm10 clear 16 timer register tm1 compare register cm10 remark f clk : internal system clock
m pd78363a, 78365a, 78366a, 78368a 40 figure 3-9. block diagram of timer 2 4-point sampling noise rejection circuit timer register tm2 capture/compare register cc20 capture register ct20 16 f clk /2 2 f clk /2 3 f clk /2 4 f clk /2 5 f clk /2 6 f clk /2 8 f clk /2 9 f clk /2 10 f clk f clk /2 2 f clk /2 3 f clk /2 4 f clk /2 6 f clk /2 7 f clk /2 8 clr2 intp3/intcc20 intp3 clear remark f clk : internal system clock figure 3-10. block diagram of timer 3 4-point sampling noise rejection circuit timer register tm3 capture/compare register cc30 16 f clk /2 2 f clk /2 3 f clk /2 4 f clk /2 5 f clk /2 6 f clk /2 8 f clk f clk /2 2 f clk /2 3 f clk /2 4 clr3 intp0/intcc30 intp0 4-point sampling noise rejection circuit capture register ct30 f clk f clk /2 2 f clk /2 3 f clk /2 4 intp1 intp1 4-point sampling noise rejection circuit f clk f clk /2 2 f clk /2 3 f clk /2 4 intp4 intp4 intov3 clear capture register ct31 remark f clk : internal system clock
m pd78363a, 78365a, 78366a, 78368a 41 figure 3-11. block diagram of timer 4 (general-purpose timer mode) f clk f clk /2 f clk /4 f clk /8 f clk /16 f clk /32 timer register tm4 compare register cm40 compare register cm41 clear intcm40 q s 16 r intcm41 alv40 to40 remark f clk : internal system clock figure 3-12. block diagram of timer 4 (udc mode) f clk /4 f clk /8 f clk /16 timer register tm4 intcm40 tclrud compare register cm40 compare register cm41 up/down detector tiud clear 16 intcm41 tcud ovf udf pre-set remark f clk : internal system clock
m pd78363a, 78365a, 78366a, 78368a 42 3.7 real-time output port (rtp) the real-time output port is a 4-bit port that can output the contents of the real-time output port register (rtp) in synchronization with the trigger signal from the real-time pulse unit (rpu). it can output synchronization pulses of multiple channels. also, pwm modulation can be applied to p00-p03. figure 3-13. block diagram of real-time output port 4 4 rtp p03p02 p01p00 pwm0 pwm1 internal bus intcm03 (from rpu) intcm10 (from rpu) intp0/intcc30 (from rpu) software trigger output trigger control circuit rtpm pwm signal control circuit output latch (p03-p00)
m pd78363a, 78365a, 78366a, 78368a 43 3.8 a/d converter the m pd78366a contains a high-speed, high-resolution 10-bit analog-to-digital (a/d) converter (conversion time 12.6 m s at an internal clock frequency of 16 mhz). successive approximation type is adopted. this converter is provided with eight analog input lines (ani0-ani7) and can perform various operations as the application requires, in select, scan, and mixed modes. when a/d conversion ends, an internal interrupt (intad) occurs. this interrupt can start a macro service that executes automatic data transfer through hardware. figure 3-14. block diagram of a/d converter adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 adm (8) 10 8 9 90 0 10 10 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 intcm03 intp2 av dd av ref av ss sar (10) input curcuit sample & hold resistor string comparator controller (start trigger) internal bus
m pd78363a, 78365a, 78366a, 78368a 44 3.9 serial interface the m pd78366a is provided with the following two independent serial interfaces: ? asynchronous serial interface (uart) (with pin selection function) ? clocked serial interface ? 3-line serial i/o mode ? serial bus interface mode (sbi mode) since the m pd78366a contains a baud rate generator (brg), any serial transfer rate can be set regardless of the operating clock frequency. the baud rate generator is a block to generate the shift clock for the transmit/ receive serial interface, and is used commonly with the two channels of the serial interfaces. the serial transfer rate can be selected in a range of 110 bps to 38.4 kbps by the mode register. figure 3-15. block diagram of asynchronous serial interface sps r x d0 r x d1 t x d0 t x d1 sps rxb pe fe ove rxe ps1 ps0 cl sl sps sck asim txs asis intsr intser intst 1 16 1 16 f clk /8 internal bus receive buffer receive shift register receive control parity check selector selector transfer shift register transfer control parity append transfer/ receive baud rate generator output selector
m pd78363a, 78365a, 78366a, 78368a 45 figure 3-16. block diagram of clocked serial interface ctxe si/sb1 so/sb0 mod1 mod2 mod1 sck mod1 mod2 wup intcsi 1/2 f clk /8 f clk /32 cls0 cls1 cmdt relt sbic mod1 mod2 wup crxe mod0 cls1 cls0 bsye cmdd ackt acke ackd reld cmdt relt 8 8 8 0 7 d q internal bus shift register (sio) so latch busy/ acknow- ledge detector circuit bus release/ command/ acknowledge detector circuit serial clock counter interrupt signal generation control circuit serial clock control circuit baud rate generator (brg) selector selector selector csim figure 3-17. block diagram of baud rate generator 70 70 brg brgc f clk /2 tmbrg 1 2 clear serial interface internal bus coincidence prescaler
m pd78363a, 78365a, 78366a, 78368a 46 3.10 pwm unit the m pd78366a is provided with two lines that output 8-/9-/10-/12-bit resolution variable pwm signals. the pwm output can be used as a digital-to-analog conversion output by connecting an external lowpass filter, and ideal for controlling actuators such as motors. an output of between 244 hz and 62.5 khz can be obtaind, depending on the combination of the count clock (62.5 ns to 1 m s) and counter bit length (8, 9, 10, or 12) (at an internal clock frequency of 16 mhz). figure 3-18. block diagram of pwm unit 7 8 9 11 0-7 0-8 0-9 0-11 counter (12) f clk /16 f clk /8 f clk /4 f clk /2 f clk overflow s r q alvn pwmn comparator (12) compare register cmpn (12) pwm buffer register n (12) coinci- dence remark n = 0, 1
m pd78363a, 78365a, 78366a, 78368a 47 3.11 watchdog timer (wdt) the watchdog timer is a free running timer equipped with a non-maskable interrupt function to prevent program hang-up or deadlock. when an error of the program is detected, the overflow interrupt (intwdt) of the watchdog timer occurs and the watchdog timer output pin (wdto) goes low. by connecting this output pin to the reset pin, any malfunctioning of the application system due to program error can be prevented. figure 3-19. block diagram of watchdog timer f clk /2 13 f clk /2 11 f clk /2 9 wdt clr wdt stop clear overflow clear f clk intwdt timer (5 bits) s r q wdto overflow watchdog timer (8 bits) oscillation stabilization time control circuit
m pd78363a, 78365a, 78366a, 78368a 48 4. interrupt functions 4.1 outline the m pd78366a is provided with powerful interrupt functions that can process interrupt requests from the internal hardware peripherals and external sources. in addition, the following three interrupt processing modes are available. in addition, four levels of interrupt priority can be specified. ? vectored interrupt processing ? macro service ? context switching table 4-1. interrupt sources note C C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C C C C interrupt source name trigger nmi nmi pin input intwdt watchdog timer intov3 overflow of timer 3 intp0/intcc30 intp0 pin input/cc30 coincidence signal intp1 intp1 pin input intp2 intp2 pin input intp3/intcc20 intp3 pin input/cc20 coincidence signal intp4 intp4 pin input inttm0 underflow of timer 0 intcm03 cm03 coincidence signal intcm10 cm10 coincidence signal intcm40 cm40 coincidence signal intcm41 cm41 coincidence signal intser receive error of uart intsr end of uart reception intst end of uart transfer intcsi end of csi transfer/reception intad end of a/d conversion brk brk instruction brkcs brkcs instruction trap illegal op code trap reset reset input source unit external wdt rpu external/rpu external external/rpu external rpu uart csi a/d C C C C vector table address 0002h 0004h 0006h 0008h 000ah 000ch 000eh 0010h 0012h 0014h 0016h 0018h 001ah 001ch 001eh 0020h 0022h 0024h 003eh C 003ch 0000h macro service none provided none context switching none provided none provided none type non- maskable maskable software exception reset note default priority : priority that takes precedence when two or more maskable interrupts occur at the same time. 0 is the highest priority, and 15 is the lowest.
m pd78363a, 78365a, 78366a, 78368a 49 4.2 macro service the m pd78366a has a total of five macro services. each macro service is described below. (1) counter mode: evtcnt ? operation (a) increments or decrements an 8-bit macro service counter (msc). (b) a vector interrupt request is generated when msc reaches 0. msc +1/? ? application example: as event counter, or to measure number of times a value is captured (2) block transfer mode: blktrs ? operation (a) transfers data block between a buffer and a sfr specified by sfr pointer (sfrp). (b) the transfer source and destination can be in sfr or buffer area. the length of the transfer data can be specified to be byte or word. (c) the number of times the data is to be transferred (block size) is specified by msc. (d) msc is auto decremented by one each time the macro service has been executed. (e) when msc reaches 0, a vector interrupt request is generated. ? sfrp msc sfr buffer n buffer 1 internal bus ? application example: to transfer/receive data through serial interface
m pd78363a, 78365a, 78366a, 78368a 50 (3) block transfer mode (with memory pointer): blktrs-p ? operation this is the block transfer mode in (2) above with a memory pointer (memp). the appended buffer area of memp can be freely set on the memory space. remark each time the macro service is executed, memp is auto incremented (by one for byte data transfer and by two for word data transfer). ? sfrp msc sfr memp +1/+2 buffer n buffer 1 internal bus ? application example: same as (2) (4) data differential mode: dtadif ? operation (a) calculates the difference between the contents of sfr (current value) specified by sfrp and the contents of sfr saved to the last data buffer (ldb). (b) stores the result of the calculation in a predetermined buffer area. (c) stores the contents of the current value of the sfr in ldb. (d) the number of times the data is to be transferred (block size) is specified by msc. each time the macro service is executed, msc is auto decremented by one. (e) when msc reaches 0, a vector interrupt request is generated. remark the differential calculation can be carried out only with 16-bit sfrs. ? sfr ldb buffer n buffer 1 differential calculation internal bus sfrp msc ? application example : to measure cycle and pulse width by the capture register of the real-time pulse unit (rpu)
m pd78363a, 78365a, 78366a, 78368a 51 (5) data differential mode (with memory pointer): dtadif-p ? operation this is the data differential mode in (4) above with memory pointer (memp). by appending memp, the buffer area in which the differential data is to be stored can be set freely on the memory space. remarks 1. the differential calculation can be carried out only with 16-bit sfrs. 2. the buffer is specified by the result of operation by memp and msc note . memp is not updated after the data has been transferred. note memp C (msc 2) + 2 ? sfr memp ldb sfrp msc buffer n buffer 1 differential calculation internal bus ? application example: same as (4)
m pd78363a, 78365a, 78366a, 78368a 52 4.3 context switching this function is to select a specific register bank through the hardware, and to branch execution to a vector address predetermined in the register bank. at the same time, it saves the present contents of the pc and psw to the register bank when an interrupt occurs, or when the brkcs instruction is executed. 4.3.1 context switching function by interrupt request when a context switching enable flag corresponding to each maskable interrupt request is set to 1 in the ei (interrupt enable) status, the context switching function can be started. the context switching operation by an interrupt request is performed as follows: (1) when an interrupt request is generated, a register bank to which the context is to be switched is specified by the contents of the low-order 3 bits of the row address (even address) of the corresponding vector table. (2) a predetermined vector address is transferred to the pc in the register bank to which the context is to be switched, and the contents of the pc and psw immediately before the switching takes place are saved to the register bank. (3) execution branches to an address indicated by the contents of the pc newly set. figure 4-1. operation of context switching pc psw rp0 rp1 rp2 rp3 rp4 rp5 rp6 rp7 register bank register bank (0-7) exchange save
m pd78363a, 78365a, 78366a, 78368a 53 4.3.2 context switching function by brkcs instruction the context switching function can be started by the brkcs instruction. the operation of context switching by an interrupt request is as follows: (1) an 8-bit register is specified by the operand of the brkcs instruction, and the register bank to which the context is to be switched is specified by the contents of this register (only the low-order 3 bits of 8 bits are valid). (2) the vector address predetermined in the register bank to which the context is to be switched is transferred to the pc, and at the same time, the contents of the pc and psw immediately before the switching takes place are saved to the register bank. (3) execution branches to the contents of the pc newly set. 4.3.3 restoration from context switching to restore from the switched context, one of the following two instructions are used. which instruction is to be executed is determined by the source that has started the context switching. table 4-2. instructions to restore from context switching restore instruction context switching starting source retcs occurrence of interrupt retcsb execution of brkcs instruction
m pd78363a, 78365a, 78366a, 78368a 54 5. external device expansion function the m pd78366a can connect external devices (data memory, program memory, and peripheral devices) in addition to the internal rom and ram areas. to connect an external device, the address/data bus and read/ write strobe signals are controlled by using ports 4, 5, and 9. table 5-1. pin function with external device connected pin function with external device connected function name multiplexed address/data bus ad0-ad7 address bus a8-a15 read strobe rd write strobe wr address strobe astb pin p40-p47 p50-p57 p90 p91 astb
m pd78363a, 78365a, 78366a, 78368a 55 6. standby functions the m pd78366a is provided with standby functions to reduce the power consumption of the system. the standby functions can be effected in the following two modes: ? halt mode ..... in this mode, the operating clock of the cpu is stopped. by using this mode in combination with an ordinary operation mode, the m pd78366a operates intermittently to reduce the total power consumption of the system. ? stop mode .... in this mode, the oscillator is stopped, and therefore the entire system is stopped. therefore, power consumption can be minimized with only a leakage current flowing. each mode is set through software. figure 6-1 shows the transition of the status in the standby modes (stop and halt modes). figure 6-1. transition of standby status stop halt ordinary stop set reset released nmi halt set reset released unmasked interrupt occurs
m pd78363a, 78365a, 78366a, 78368a 56 7. reset function when a low level is input to the reset pin, the system is reset, and each hardware enters the initial status (reset status). when the reset pin goes high, the reset status is released, and program execution is started. initialize the contents of each register through program as necessary. especially, change the number of cycles of the programmable wait control register as necessary. the reset pin is equipped with a noise rejecter circuit of analog delay to prevent malfunctioning due to noise. cautions 1. while the reset pin is active (low level), all the pins go into a high-impedance state (except wdto, av ref , av dd , av ss , v dd , v ss , x1, and x2 pins). 2. when an external ram is connected, do not connect a pull-up resistor to the p90/rd and p91/wr pins, because the p90/rd and p91/wr pins may go into a high-impedance state, resulting in destruction of the contents of the external ram. in addition, signal contention occurs on the address/data bus, resulting in damage to the input/output circuit. figure 7-1. accepting reset signal reset input analog delay analog delay analog delay rejected as noise reset accepted reset released to effect reset on when power is applied, make sure that sufficient time elapses to stabilize the oscillation after the power is applied until the reset signal is accepted, as shown in figure 7-2. figure 7-2. reset on power application v dd reset oscillation stabilization time analog delay reset released
m pd78363a, 78365a, 78366a, 78368a 57 8. instruction set write an operand in the operand field of each instruction according to the description of the instruction (for details, refer to the assembler specifications). some instructions have two or more operands. select one of them. uppercase characters, +, C, #, $, !, [, and ] are keywords and must be written as is. write an appropriate numeric value or label as immediate data. to write a label, be sure to write #, $, !, [, or ]. table 8-1. operand representation and description description r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15 r0, r1, r2, r3, r4, r5, r6, r7 c, b rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7 rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7 de, hl, vp, up special function register symbol (refer to table 2-1 .) special function register symbol (register that can be manipulated in 16-bit units. refer to table 2-1 .) rp0, rp1, rp2, rp3, rp4, rp5/psw, rp6, rp7 (more than one symbol can be written. however, rp5 can be written only for push and pop instructions, and psw can be written only for pushu and popu instructions.) [de], [hl], [de+], [hl+], [deC], [hlC], [vp], [up] ; register indirect mode [de + a], [hl + a], [de + b], [hl + b], [vp + de], [vp + hl] ; based indexed mode [de + byte], [hl + byte], [vp + byte], [up + byte], [sp + byte] ; based mode word[a], word[b], word[de], word[hl] ; indexed mode fe20h-ff1fh immediate data or label fe20h-ff1eh immediate data (however, bit0 = 0) or label (manipulated in 16-bit units) 0000h-fdffh immediate data or label; relative addressing 0000h-fdffh immediate data or label; immediate addressing (however, up to ffffh can be written for mov instruction. only fe00h-feffh can be written for movtblw instruction.) 800h-fffh immediate data or label 40h-7eh immediate data (however, bit0 = 0) note or label 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label 3-bit immediate data (0-7) representation r r1 r2 rp rp1 rp2 sfr sfrp post mem saddr saddrp $ addr16 ! addr16 addr11 addr5 word byte bit n note do not access bit0 = 1 (odd address) in word units. remarks 1. rp and rp1 are the same in terms of register name that can be written but are different in code to be generated. 2. r, r1, rp, rp1, and post can be written in absolute name (r0-r15, rp0-rp7) and function name (x, a, c, b, e, d, l, h, ax, bc, de, hl, vp, and up). 3. immediate addressing can address the entire space. relative addressing can address only a range of C128 to +127 from the first address of the next instruction.
m pd78363a, 78365a, 78366a, 78368a 58 mnemonic operand byte operation flag s z ac p/v cy mov xch instructions 8-bit data transfer r1, #byte 2 saddr, #byte 3 sfr note , #byte 3 r, r1 2 a, r1 1 a, saddr 2 saddr, a 2 saddr, saddr 3 a, sfr 2 sfr, a 2 a, mem 1-4 mem, a 1-4 a, [saddrp] 2 [saddrp], a 2 a, !addr16 4 !addri16, a 4 pswl, #byte 3 pswh, #byte 3 pswl, a 2 pswh, a 2 a, pswl 2 a, pswh 2 a, r1 1 r, r1 2 a, mem 2-4 a, saddr 2 a, sfr 3 a, [saddrp] 2 saddr, saddr 3 r1 ? byte (saddr) ? byte sfr ? byte r ? r1 a ? r1 a ? (saddr) (saddr) ? a (saddr) ? (saddr) a ? sfr sfr ? a a ? (mem) (mem) ? a a ? ((saddrp)) ((saddrp)) ? a a ? (addr16) (addr16) ? a psw l ? byte psw h ? byte psw l ? a psw h ? a a ? psw l a ? psw h a ? r1 r ? r1 a ? (mem) a ? (saddr) a ? sfr a ? ((saddrp)) (saddr) ? (saddr) note when stbc or wdm is written as sfr, this instruction is treated as a dedicated instruction whose number of bytes is different from that of this instruction. remark for symbols in flag, refer to the table below. symbol remarks (blank) no change 0 cleared to 0 1 set to 1 set/cleared according to result p p/v flag functions as parity flag v p/v flag operates as overflow flag r value previously saved is restored
m pd78363a, 78365a, 78366a, 78368a 59 flag s z ac p/v cy mnemonic operand byte operation instructions 16-bit data transfer 8-bit operation rp1, #word 3 saddrp, #word 4 sfrp, #word 4 rp, rp1 2 ax, saddrp 2 saddrp, ax 2 saddrp, saddrp 3 ax, sfrp 2 sfrp, ax 2 rp1, !addr16 4 !addr16, rp1 4 ax, mem 2-4 mem, ax 2-4 ax, saddrp 2 ax, sfrp 3 saddrp, saddrp 3 rp, rp1 2 ax, mem 2-4 a, #byte 2 saddr, #byte 3 sfr, #byte 4 r, r1 2 a, saddr 2 a, sfr 3 saddr, saddr 3 a, mem 2-4 mem, a 2-4 a, #byte 2 saddr, #byte 3 sfr, #byte 4 r, r1 2 a, saddr 2 a, sfr 3 saddr, saddr 3 a, mem 2-4 mem, a 2-4 rp1 ? word (saddrp) ? word sfrp ? word rp ? rp1 ax ? (saddrp) (saddrp) ? ax (saddrp) ? (saddrp) ax ? sfrp sfrp ? ax rp1 ? (addr16) (addr16) ? rp1 ax ? (mem) (mem) ? ax ax ? (saddrp) ax ? sfrp (saddrp) ? (saddrp) rp ? rp1 ax ? (mem) a, cy ? a + byte (saddr), cy ? (saddr) + byte sfr, cy ? sfr + byte r, cy ? r + r1 a, cy ? a + (saddr) a, cy ? a + sfr (saddr), cy ? (saddr) + (saddr) a, cy ? a + (mem) (mem), cy ? (mem) + a a, cy ? a + byte + cy (saddr), cy ? (saddr) + byte + cy sfr, cy ? sfr + byte + cy r, cy ? r + r1 + cy a, cy ? a + (saddr) + cy a, cy ? a + sfr + cy (saddr), cy ? (saddr) + (saddr) + cy a, cy ? a + (mem) + cy (mem), cy ? (mem) + a + cy v v v v v v v v v v v v v v v v v v movw xchw add addc
m pd78363a, 78365a, 78366a, 78368a 60 flag s z ac p/v cy a, cy ? a C byte (saddr), cy ? (saddr) C byte sfr, cy ? sfr C byte r, cy ? r C r1 a, cy ? a C (saddr) a, cy ? a C sfr (saddr), cy ? (saddr) C (saddr) a, cy ? a C (mem) (mem), cy ? (mem) C a a, cy ? a C byte C cy (saddr), cy ? (saddr) C byte C cy sfr, cy ? sfr C byte C cy r, cy ? r C r1 C cy a, cy ? a C (saddr) C cy a, cy ? a C sfr C cy (saddr), cy ? (saddr) C (saddr) C cy a, cy ? a C (mem) C cy (mem), cy ? (mem) C a C cy a ? a byte (saddr) ? (saddr) byte sfr ? sfr byte r ? r r1 a ? a (saddr) a ? a sfr (saddr) ? (saddr) (saddr) a ? a (mem) (mem) ? (mem) a v v v v v v v v v v v v v v v v v v p p p p p p p p p mnemonic operand byte operation instructions sub subc and 8-bit operation a, #byte 2 saddr, #byte 3 sfr, #byte 4 r, r1 2 a, saddr 2 a, sfr 3 saddr, saddr 3 a, mem 2-4 mem, a 2-4 a, #byte 2 saddr, #byte 3 sfr, #byte 4 r, r1 2 a, saddr 2 a, sfr 3 saddr, saddr 3 a, mem 2-4 mem, a 2-4 a, #byte 2 saddr, #byte 3 sfr, #byte 4 r, r1 2 a, saddr 2 a, sfr 3 saddr, saddr 3 a, mem 2-4 mem, a 2-4
m pd78363a, 78365a, 78366a, 78368a 61 flag s z ac p/v cy a, #byte 2 saddr, #byte 3 sfr, #byte 4 r, r1 2 a, saddr 2 a, sfr 3 saddr, saddr 3 a, mem 2-4 mem, a 2-4 a, #byte 2 saddr, #byte 3 sfr, #byte 4 r, r1 2 a, saddr 2 a, sfr 3 saddr, saddr 3 a, mem 2-4 mem, a 2-4 a, #byte 2 saddr, #byte 3 sfr, #byte 4 r, r1 2 a, saddr 2 a, sfr 3 saddr, saddr 3 a, mem 2-4 mem, a 2-4 a ? a byte (saddr) ? (saddr) byte sfr ? sfr byte r, ? r r1 a ? a (saddr) a ? a sfr (saddr) ? (saddr) (saddr) a ? a (mem) (mem) ? (mem) M a a ? a byte (saddr) ? (saddr) byte sfr ? sfr byte r ? r r1 a ? a (saddr) a ? a sfr (saddr) ? (saddr) (saddr) a ? a (mem) (mem) ? (mem) a a C byte (saddr) C byte sfr C byte r C r1 a C (saddr) a C sfr (saddr) C (saddr) a C (mem) (mem) C a p p p p p p p p p p p p p p p p p p v v v v v v v v v mnemonic operand byte operation instructions or xor cmp 8-bit operation
m pd78363a, 78365a, 78366a, 78368a 62 flag s z ac p/v cy mnemonic operand byte operation instructions multiplication /division relative operation signed multipli- cation sum-of- products operation sum-of-products operation with saturation addw subw cmpw mulu divuw muluw divux mulw macw macsw sacw ax, #word 3 saddrp, #word 4 sfrp, #word 5 rp, rp1 2 ax, saddrp 2 ax, sfrp 3 saddrp, saddrp 3 ax, #word 3 saddrp, #word 4 sfrp, #word 5 rp, rp1 2 ax, saddrp 2 ax, sfrp 3 saddrp, saddrp 3 ax, #word 3 saddrp, #word 4 sfrp, #word 5 rp, rp1 2 ax, saddrp 2 ax, sfrp 3 saddrp, saddrp 3 r1 2 r1 2 rp1 2 rp1 2 rp1 2 n3 n3 [de + ], [hl + ] 4 ax, cy ? ax + word (saddrp), cy ? (saddrp) + word sfrp, cy ? sfrp + word rp, cy ? rp + rp1 ax, cy ? ax + (saddrp) ax, cy ? ax + sfrp (saddrp), cy ? (saddrp) + (saddrp) ax, cy ? ax C word (saddrp), cy ? (saddrp) C word sfrp, cy ? sfrp C word rp, cy ? rp C rp1 ax, cy ? ax C (saddrp) ax, cy ? ax C sfrp (saddrp), cy ? (saddrp) C (saddrp) ax C word (saddrp) C word sfrp C word rp C rp1 ax C (saddrp) ax C sfrp (saddrp) C (saddrp) ax ? ax r1 ax (quotient), r1 (remainder) ? ax ? r1 ax (high-order 16 bits), rp1 (low-order 16 bits) ? ax rp1 axde (quotient), rp1 (remainder) ? axde ? rp1 ax (high-order 16 bits), rp1 (low-order 16 bits) ? ax rp1 axde ? (b) (c) + axde b ? b + 2, c ? c + 2, n ? n C 1 end if n = 0 or p/v = 1 axde ? (b) (c) + axde b ? b + 2, c ? c + 2, n ? n C 1 if overflow (p/v = 1) then axde ? 7fffffffh if underflow (p/v = 1) then axde ? 80000000h end if n = 0 or p/v = 1 ax ? ax + | (de) C (hl) | de ? de + 2 hl ? hl + 2 c ? c C 1 end if c = 0 or cy = 1 v v v v v v v v v v v v v v v v v v v v v v v v 16-bit operation
m pd78363a, 78365a, 78366a, 78368a 63 r1 1 saddr 2 r1 1 saddr 2 rp2 1 saddrp 3 rp2 1 saddrp 3 r1, n 2 r1, n 2 r1, n 2 r1, n 2 r1, n 2 r1, n 2 rp1, n 2 rp1, n 2 [rp1] 2 [rp1] 2 2 1 flag s z ac p/v cy mnemonic operand byte operation instructions movtblw inc dec incw decw ror rol rorc rolc shr shl shrw shlw ror4 rol4 adjba adjbs cvtbw (addr16 + 2) ? (addr16), n ? n C 1 addr16 ? addr16 C 2, end if n = 0 r1 ? r1 + 1 (saddr) ? (saddr) + 1 r1 ? r1 C 1 (saddr) ? (saddr) C 1 rp2 ? rp2 + 1 (saddrp) ? (saddrp) + 1 rp2 ? rp2 C 1 (saddrp) ? (saddrp) C 1 (cy, r1 7 ? r1 0 , r1 mC1 ? r1 m ) n times (cy, r1 0 ? r1 7 , r1 m+1 ? r1 m ) n times (cy ? r1 0 , r1 7 ? cy, r1 mC1 ? r1 m ) n times (cy ? r1 7 , r1 0 ? cy, r1 m+1 ? r1 m ) n times (cy ? r1 0 , r1 7 ? 0, r1 mC1 ? r1 m ) n times (cy ? r1 7 , r1 0 ? 0, r1 m+1 ? r1 m ) n times (cy ? rp1 0 , rp1 15 ? 0, rp1 mC1 ? rp1 m ) n times (cy ? rp1 15 , rp1 0 ? 0, rp1 m+1 ? rp1 m ) n times a 3C0 ? (rp1) 3C0 , (rp1) 7C4 ? a 3C0 , (rp1) 3C0 ? (rp1) 7C4 a 3C0 ? (rp1) 7C4 , (rp1) 3C0 ? a 3C0 , (rp1) 7C4 ? (rp1) 3C0 decimal adjust accumelator when a 7 = 0, x ? a, a ? 00h when a 7 = 1, x ? a, a ? ffh table shift v v v v p p p p 0p 0p 0p 0p 0p increment/decrement bcd adjustment data conversion shift rotate !addr16, n 4 remarks 1. n of the shift rotate instruction indicates the number of times the shift rotate instruction is executed. 2. the address of the table shift instruction ranges from fe00h to feffh.
m pd78363a, 78365a, 78366a, 78368a 64 mnemonic operand byte operation flag s z ac p/v cy instructions cy, saddr.bit 3 cy, sfr.bit 3 cy, a.bit 2 cy, x.bit 2 cy, pswh.bit 2 cy, pswl.bit 2 saddr.bit, cy 3 sfr.bit, cy 3 a.bit, cy 2 x.bit, cy 2 pswh.bit, cy 2 pswl.bit, cy 2 cy, saddr.bit 3 cy, /saddr.bit 3 cy, sfr.bit 3 cy, /sfr.bit 3 cy, a.bit 2 cy, /a.bit 2 cy, x.bit 2 cy, /x.bit 2 cy, pswh.bit 2 cy, /pswh.bit 2 cy, pswl.bit 2 cy, /pswl.bit 2 cy, saddr.bit 3 cy, /saddr.bit 3 cy, sfr.bit 3 cy, /sfr.bit 3 cy, a.bit 2 cy, /a.bit 2 cy, x.bit 2 cy, /x.bit 2 cy, pswh.bit 2 cy, /pswh.bit 2 cy, pswl.bit 2 cy, /pswl.bit 2 cy ? (saddr.bit) cy ? sfr.bit cy ? a.bit cy ? x.bit cy ? psw h .bit cy ? psw l .bit (saddr.bit) ? cy sfr.bit ? cy a.bit ? cy x.bit ? cy psw h .bit ? cy psw l .bit ? cy cy ? cy (saddr.bit) cy ? cy (saddr.bit) cy ? cy sfr.bit cy ? cy sfr.bit cy ? cy a.bit cy ? cy a.bit cy ? cy x.bit cy ? cy x.bit cy ? cy psw h .bit cy ? cy psw h .bit cy ? cy psw l .bit cy ? cy psw l .bit cy ? cy (saddr.bit) cy ? cy (saddr.bit) cy ? cy sfr.bit cy ? cy sfr.bit cy ? cy a.bit cy ? cy a.bit cy ? cy x.bit cy ? cy x.bit cy ? cy psw h .bit cy ? cy psw h .bit cy ? cy psw l .bit cy ? cy psw l .bit mov1 and1 or1 bit manipulation
m pd78363a, 78365a, 78366a, 78368a 65 mnemonic operand byte operation flag s z ac p/v cy instructions cy, saddr.bit 3 cy, sfr.bit 3 cy, a.bit 2 cy, x.bit 2 cy, pswh.bit 2 cy, pswl.bit 2 saddr.bit 2 sfr.bit 3 a.bit 2 x.bit 2 pswh.bit 2 pswl.bit 2 saddr.bit 2 sfr.bit 3 a.bit 2 x.bit 2 pswh.bit 2 pswl.bit 2 saddr.bit 3 sfr.bit 3 a.bit 2 x.bit 2 pswh.bit 2 pswl.bit 2 cy 1 cy 1 cy 1 cy ? cy (saddr.bit) cy ? cy sfr.bit cy ? cy a.bit cy ? cy x.bit cy ? cy psw h .bit cy ? cy psw l .bit (saddr.bit) ? 1 sfr.bit ? 1 a.bit ? 1 x.bit ? 1 psw h .bit ? 1 psw l .bit ? 1 (saddr.bit) ? 0 sfr.bit ? 0 a.bit ? 0 x.bit ? 0 psw h .bit ? 0 psw l .bit ? 0 (saddr.bit) ? (saddr.bit) sfr.bit ? sfr.bit a.bit ? a.bit x.bit ? x.bit psw h .bit ? psw h .bit psw l .bit ? psw l .bit cy ? 1 cy ? 0 cy ? cy 1 0 xor1 set1 clr1 not1 set1 clr1 not1 bit manipulation
m pd78363a, 78365a, 78366a, 78368a 66 mnemonic operand byte operation flag s z ac p/v cy instructions (sp C 1) ? (pc + 3) h , (sp C 2) ? (pc + 3) l , pc ? addr16, sp ? sp C 2 (sp C 1) ? (pc + 2) h , (sp C 2) ? (pc + 2) l , pc 15 C 11 ? 00001, pc 10 C 0 ? addr11, sp ? sp C 2 (sp C 1) ? (pc + 1) h , (sp C 2) ? (pc + 1) l , pc h ? (tpf, 00000000, addr5 + 1), pc l ? (tpf, 00000000, addr5 ), sp ? sp C 2 (sp C 1) ? (pc + 2) h , (sp C 2) ? (pc + 2) l , pc h ? rp1 h , pc l ? rp1 l , sp ? sp C 2 (sp C 1) ? (pc + 2) h , (sp C 2) ? (pc + 2) l , pc h ? (rp1 + 1), pc l ? (rp1), sp ? sp C 2 (sp C 1) ? psw h , (sp C 2) ? psw l (sp C 3) ? (pc + 1) h , (sp C 4) ? (pc + 1) l , pc l ? (003eh), pc h ? (003fh), sp ? sp C 4, ie ? 0 pc l ? (sp), pc h ? (sp + 1), sp ? sp + 2 pc l ? (sp), pc h ? (sp +1) psw l ? (sp + 2), psw h ? (sp + 3) sp ? sp + 4 pc l ? (sp), pc h ? (sp + 1) psw l ? (sp + 2), psw h ? (sp + 3) sp ? sp + 4 (sp C 1) ? sfr h (sp C 2) ? sfr l sp ? sp C 2 {(sp C 1) ? post h , (sp C 2) ? post l , sp ? sp C 2} n times (sp C 1) ? psw h , (sp C 2) ? psw l , sp ? sp C 2 {(up C 1) ? post h , (up C 2) ? post l , up ? up C 2} n times sfr l ? (sp) sfr h ? (sp + 1) sp ? sp + 2 {post l ? (sp), post h ? (sp + 1), sp ? sp + 2} n times psw l ? (sp), psw h ? (sp + 1), sp ? sp + 2 {post l ? (up),post h ? (up + 1), up ? up + 2} n times sp ? word sp ? ax ax ? sp sp ? sp + 1 sp ? sp C 1 stack manipulation call/return !addr16 3 !addr11 2 [addr5] 1 rp1 2 [rp1] 2 1 1 1 1 sfrp 3 post 2 psw 1 post 2 sfrp 3 post 2 psw 1 post 2 sp, #word 4 sp, ax 2 ax, sp 2 sp 2 sp 2 rrrrr rrrrr rrrrr call callf callt call brk ret retb reti push pushu pop popu movw incw decw remark n of the stack manipulation instruction is the number of registers written as post.
m pd78363a, 78365a, 78366a, 78368a 67 (pin level) (signal level before output buffer) a ? (pin level) (signal level before output buffer) pc ? addr16 pc h ? rp1 h , pc l ? rp1 l pc h ? (rp1 + 1), pc l ? (rp1) pc ? pc + 2 + jdisp8 pc ? pc + 2 + jdisp8 if cy = 1 pc ? pc + 2 + jdisp8 if cy = 0 pc ? pc + 2 + jdisp8 if z = 1 pc ? pc + 2 + jdisp8 if z = 0 pc ? pc + 2 + jdisp8 if p/v = 1 pc ? pc + 2 + jdisp8 if p/v = 0 pc ? pc + 2 + jdisp8 if s = 1 pc ? pc + 2 + jdisp8 if s = 0 pc ? pc + 3 + jdisp8 if (p/v s) M z = 0 pc ? pc + 3 + jdisp8 if p/v s= 0 pc ? pc + 3 + jdisp8 if p/v s = 1 pc ? pc + 3 + jdisp8 if (p/v s) M z = 1 pc ? pc + 3 + jdisp8 if z cy = 0 pc ? pc + 3 + jdisp8 if z cy = 1 pc ? pc + 3 + jdisp8 if (saddr.bit) = 1 pc ? pc + 4 + jdisp8 if sfr.bit = 1 pc ? pc + 3 + jdisp8 if a.bit = 1 pc ? pc + 3 + jdisp8 if x.bit = 1 pc ? pc + 3 + jdisp8 if psw h .bit = 1 pc ? pc + 3 + jdisp8 if psw l .bit = 1 pc ? pc + 4 + jdisp8 if (saddr.bit) = 0 pc ? pc + 4 + jdisp8 if sfr.bit = 0 pc ? pc + 3 + jdisp8 if a.bit = 0 pc ? pc + 3 + jdisp8 if x.bit = 0 pc ? pc + 3 + jdisp8 if psw h .bit = 0 pc ? pc + 3 + jdisp8 if psw l .bit = 0 flag s z ac p/v cy mnemonic operand byte operation instructions special unconditional branch conditional branch chkl chkla br bc bl bnc bnl bz be bnz bne bv bpe bnv bpo bn bp bgt bge blt ble bh bnh bt bf p p sfr 3 sfr 3 !addr16 3 rp1 2 [rp1] 2 $addr16 2 $addr16 2 $addr16 2 $addr16 2 $addr16 2 $addr16 2 $addr16 2 $addr16 2 $addr16 2 $addr16 3 $addr16 3 $addr16 3 $addr16 3 $addr16 3 $addr16 3 saddr.bit, $addr16 3 sfr.bit, $addr16 4 a.bit, $addr16 3 x.bit, $addr16 3 pswh.bit, $addr16 3 pswl.bit, $addr16 3 saddr.bit, $addr16 4 sfr.bit, $addr16 4 a.bit, $addr16 3 x.bit, $addr16 3 pswh.bit, $addr16 3 pswl.bit, $addr16 3
m pd78363a, 78365a, 78366a, 78368a 68 flag s z ac p/v cy mnemonic operand byte operation instructions btclr bfset dbnz brkcs retcs retcsb context switching conditional branch pc ? pc + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) pc ? pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit pc ? pc + 3 + jdisp8 if a.bit = 1 then reset a.bit pc ? pc + 3 + jdisp8 if x.bit = 1 then reset x.bit pc ? pc + 3 + jdisp8 if psw h .bit = 1 then reset psw h .bit pc ? pc + 3 + jdisp8 if psw l .bit = 1 then reset psw l .bit pc ? pc + 4 + jdisp8 if (saddr.bit) = 0 then set (saddr.bit) pc ? pc + 4 + jdisp8 if sfr.bit = 0 then set sfr.bit pc ? pc + 3 + jdisp8 if a.bit = 0 then set a.bit pc ? pc + 3 + jdisp8 if x.bit = 0 then set x.bit pc ? pc + 3 + jdisp8 if psw h .bit = 0 then set psw h .bit pc ? pc + 3 + jdisp8 if psw l .bit = 0 then set psw l .bit r2 ? r2 C 1, then pc ? pc + 2 + jdisp8 if 2 1 0 (saddr) ? (saddr) C 1, then pc ? pc + 3 + jdisp8 if (saddr) 1 0 pc h ? r5, pc l ? r4, r7 ? psw h , r6 ? psw l , ? rbs2 C 0 ? n, rss ? 0, ie ? 0 pc h ? r5, pc l ? r4, r5, r4 ? addr16 psw h ? r7, psw l ? r6 pc h ? r5, pc l ? r4, r5, r4 ? addr16 psw h ? r7, psw l ? r6 rrrrr rrrrr saddr.bit, $addr16 4 sfr.bit, $addr16 4 a.bit, $addr16 3 x.bit, $addr16 3 pswh.bit, $addr16 3 pswl.bit, $addr16 3 saddr.bit, $addr16 4 sfr.bit, $addr16 4 a.bit, $addr16 3 x.bit, $addr16 3 pswh.bit, $addr16 3 pswl.bit, $addr16 3 r2, $addr16 2 saddr, $addr16 3 rbn 2 !addr16 3 !addr16 4
m pd78363a, 78365a, 78366a, 78368a 69 flag s z ac p/v cy mnemonic operand byte operation instructions [de+], a 2 [deC], a 2 [de+], [hl+] 2 [deC], [hlC] 2 [de+], a 2 [deC], a 2 [de+], [hl+] 2 [deC], [hlC] 2 [de+], a 2 [deC], a 2 [de+], [hl+] 2 [deC], [hlC] 2 [de+], a 2 [deC], a 2 [de+], [hl+] 2 [deC], [hlC] 2 [de+], a 2 [deC], a 2 [de+], [hl+] 2 [deC], [hlC] 2 (de+) ? a, c ? c C 1 end if c = 0 (deC) ? a, c ? c C 1 end if c = 0 (de+) ? (hl+), c ? c C 1 end if c = 0 (deC) ? (hlC), c ? c C 1 end if c = 0 (de+) ? a, c ? c C 1 end if c = 0 (deC) ? a, c ? c C 1 end if c = 0 (de+) ? (hl+), c ? c C 1 end if c = 0 (deC) ? (hlC), c ? c C 1 end if c = 0 (de+) C a, c ? c C 1 end if c = 0 or z = 0 (deC) C a, c ? c C 1 end if c = 0 or z = 0 (de+) C (hl+), c ? c C 1 end if c = 0 or z = 0 (deC) C (hlC), c ? c C 1 end if c = 0 or z = 0 (de+) C a, c ? c C 1 end if c = 0 or z = 1 (deC) C a, c ? c C 1 end if c = 0 or z = 1 (de+) C (hl+), c ? c C 1 end if c = 0 or z = 1 (deC) C (hlC), c ? c C 1 end if c = 0 or z = 1 (de+) C a, c ? c C 1 end if c = 0 or cy = 0 (deC) C a, c ? c C 1 end if c = 0 or cy = 0 (de+) C (hl+), c ? c C 1 end if c = 0 or cy = 0 (deC) C (hlC), c ? c C 1 end if c = 0 or cy = 0 string movm movbk xchm xchbk cmpme cmpbke cmpmne cmpbkne cmpmc cmpbkc v v v v v v v v v v v v
m pd78363a, 78365a, 78366a, 78368a 70 flag s z ac p/v cy mnemonic operand byte operation instructions (de+) C a, c ? c C 1 end if c = 0 or cy = 1 (deC) C a, c ? c C 1 end if c = 0 or cy = 1 (de+) C (hl+), c ? c C 1 end if c = 0 or cy = 1 (deC) C (hlC), c ? c C 1 end if c = 0 or cy = 1 stbc ? byte note wdm ? byte note rss ? rss rbs2 C 0 ? n, rss ? 0 rbs2 C 0 ? n, rss ? 1 no operation ie ? 1 (enable interruptt) ie ? 0 (disable interrupt) cmpmnc cmpbknc mov swrs sel nop ei di string cpu control [de+], a 2 [deC], a 2 [de+], [hl+] 2 [deC], [hlC] 2 stbc, #byte 4 wdm, #byte 4 1 rbn 2 rbn, alt 2 1 1 1 v v v v note if the op code of the stbc register and wdm register manipulation instructions is wrong, an op code trap interrupt occurs. operation on trap: (sp C 1) ? psw h , (sp C 2) ? psw l , (sp C 3) ? (pc C 4) h , (sp C 4) ? (pc C 4) l , pc l ? (003ch), pc h ? (003dh), sp ? sp C 4, ie ? 0
m pd78363a, 78365a, 78366a, 78368a 71 9. example of system configuration controlling outdoor apparatus of inverter air conditioner ani0 ani1 ani2 ani3 ani4 nmi intp1 r x d t x d p41 p40 p43 p42 p01 p00 p03 p02 u/d u v w w v u cm03 cm00 cm01 cm02 real-time pulse unit 16-bit timer dead time setting register inverter (analog signal) ac power supply monitor external temperature thermal exchange temperature outlet temperature inlet temperature dc monitor compressor motor temperature monitor 10-bit a/d converter programmable interrupt controller serial interface rom 32k bytes ram 2k bytes general- purpose port real-time output port 4-way valve 2-way valve outdoor fan motor stepping motor (electronic expansion valve) to00 to01 to02 to03 to04 to05 indoor apparatus controller pulse generation circuit pd78366a m
m pd78363a, 78365a, 78366a, 78368a 72 10. electrical specifications absolute maximum ratings (t a = 25 ?c) parameter symbol test conditions rating unit power supply voltage v dd C0.5 to +7.0 v av dd C0.5 to v dd + 0.5 v av ss C0.5 to +0.5 v input voltage v i pins other than C0.5 to v dd + 0.5 v p70/ani0-p77/ani7 output voltage v o C0.5 to v dd + 0.5 v low-level output current i ol note 20 ma output pins other than 4.0 ma those in the note total of all output pins 200 ma high-level output current i oh all output pins C3.0 ma total of all output pins C25 ma analog input voltage v ian p70/ani0-p77/ani7 pins av ss C 0.5 to av dd + 0.5 v a/d converter reference input voltage av ref av ss C 0.5 to av dd + 0.5 v operating ambient temperature t a C40 to +85 ?c storage temperature t stg C60 to +150 ?c note p00/rtp0-p03/rtp3, p04/pwm0, p05/tcud/pwm1, p06/tiud/to40, p07/tclrud, p10-p17, and p80/to00-p85/to05 pins. caution product quality may suffer if the absolute rating is exceeded for any parameter, even momentarily. in other words, an absolute maxumum rating is a value at which the possibility of psysical damage to the product cannnot be ruled out. care must therefore be taken to ensure that the these ratings are not exceeded during use of the product. recommended operating conditions oscillation frequency t a v dd 3 mhz f xx 8 mhz C40 to +85 ?c +5.0 v 10 % capacitance (t a = 25 ?c, v ss = v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c i f = 1 mhz 20 pf output capacitance c o 0 v except measured pins 20 pf i/o capacitance c io 20 pf
m pd78363a, 78365a, 78366a, 78368a 73 leave unconnected hcmos inverter x1 x2 v ss x2 x1 c1 c2 oscillator characteristics (t a = C40 to +85 ?c, v dd = +5 v 10 %, v ss = 0 v) resonator recommended circuit parameter min. max. unit ceramic resonator or oscillation frequency (f xx ) 3 8 mhz crystal resonator external clock x1 input frequency (f x ) 3 8 mhz x1 rise/fall time (t xr , t xf ) 0 30 ns x1 input high-/low-level 40 170 ns width (t wxh , t wxl ) caution when using system clock oscillation circuits, to reduce the effect of the wiring capacitouce, etc, wire the area indicated by dotted-line as follows: ? make the wiring as short as possible. ? do not allow the wiring to intersect other signal lines. keep it away from other lines in which varying high currents flow. ? make sure that the ground point of the oscillation circuit capacitor is always at the same electric potential as v ss . do not allow the wiring to be grounded to a ground pattern in which very high currents are flowing. ? do not extract signals from the oscillation circuit.
m pd78363a, 78365a, 78366a, 78368a 74 dc characteristics (t a = C40 to +85 ?c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol test conditions min. typ. max. unit low-level input voltage v il1 note 1 0 0.8 v v il2 note 2 0 0.2v dd v high-level input voltage v ih1 note 1 2.2 v v ih2 note 2 0.8v dd v low-level output voltage v ol1 note 3 i ol = 2.0 ma 0.45 v v ol2 note 4 i ol = 15 ma 1.5 v v ol3 note 5 i ol = 10 ma 1.5 v high-level output voltage v oh i oh = C400 m a v dd C 1.0 v input leakage current i li 0 v v i v dd , av dd = v dd 10 m a output leakage current i lo 0 v v o v dd , av dd = v dd 10 m a v dd supply current i dd1 operating mode 70 120 ma i dd2 halt mode 45 70 ma data retention voltage v dddr stop mode 2.5 v data retention current i dddr stop mode v dddr = 2.5 v 2 10 m a v dddr = 5.0 v 10 % 10 50 m a pull-up resistance r l v i = 0 v 15 60 150 k w notes 1. pins other than those specified in note 2 . 2. reset, x1, x2, p20/nmi, p21/intp0, p22/intp1, p23/intp2, p24/intp3/ti, p25/intp4, p32/ so/sb0, p33/si/sb1 and p34/sck pins. 3. pins other than those specified in notes 4 and 5. 4. p80/to00-p85/to05 pins (when i ol = 15 ma is in operation, up to three pins can be on simultaneously.) 5. p00/rtp0-p03/rtp3, p04/pwm0, p05/tcud/pwm1, p06/tiud/to40 and p07/tclrud pins (when i ol = 10 ma is in operation, up to four pins can be on simultaneously.) as well as p10-p17 pins (when i ol = 10 ma is in operation, up to four pins can be on simultaneously.). caution when the p80-p85, p00-p07, and p10-p17 pins are not used under the conditions specified in notes 4 and 5, they have the same characteristics as in note 3.
m pd78363a, 78365a, 78366a, 78368a 75 ac characteristics (t a = C40 to +85 ?c, v dd = +5 v 10 %, v ss = 0 v, c l = 100 pf, f xx = 8 mhz) read/write operation (when general-purpose memory is connected) parameter symbol test conditions min. max. unit system clock cycle time t cyk 62.5 166.7 ns address setup time (vs. astb )t sast 7ns address hold time (vs. astb )t hsta 11 ns rd ? address float time t fra 24 ns address ? data input time t daid 100 ns rd ? data input time t drid 49 ns astb ? rd delay time t dstr 15 ns data hold time (vs. rd - )t hrid 0ns rd - ? address active time t dra 17 ns rd low-level width t wrl 63 ns astb high-level width t wsth 14 ns wr ? data output time t dwod 21 ns astb ? wr delay time t dstw 15 ns wr - ? astb - delay time t dwst 78 ns data setup time (vs. wr - )t sodw 57 ns data hold time (vs. wr - )t hwod 8ns wr low-level width t wwl 63 ns t cyk -dependent bus timing definition parameter arithmetic expression min./max. unit t sast (0.5 + a) t C 24 min. ns t hsta 0.5t C 20 min. ns t wsth (0.5 + a) t C 17 min. ns t dstr 0.5t C 16 min. ns t wrl (1.5 + n) t C 30 min. ns t daid (2.5 + a + n) t C 56 max. ns t drid (1.5 + n) t C 44 max. ns t dra 0.5t C 14 min. ns t dstw 0.5t C 16 min. ns t dwst 1.5t C 15 min. ns t wwl (1.5 + n) t C 30 min. ns t dwod 0.5t C 10 max. ns t sodw (1 + n) t C 5 min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency.) 2. a becomes 1 when the address wait is inserted. otherwise, it becomes 0. 3. n refers to the number of wait cycles that is inserted by specifying the pwc register. 4. only the bus timings indicated in this table depend on t cyk .
m pd78363a, 78365a, 78366a, 78368a 76 serial operation (t a = C40 to +85 ?c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol test conditions min. max. unit serial clock cycle time t cysk sck output internal 8 dividing 500 ns sck input external clock 500 ns serial clock low-level t wskl sck output internal 8 dividing 210 ns width sck input external clock 210 ns serial clock high-level t wskh sck output internal 8 dividing 210 ns width sck input external clock 210 ns si setup time (vs. sck - ) t srxsk 80 ns si hold time (vs. sck - )t hskrx 80 ns sck ? so delay time t dsktx r = 1 k w , c = 100 pf 210 ns up/down counter operation (t a = C40 to +85 ?c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol test conditions min. max. unit tiud high-/low-level t wtiuh , t wtiul other than mode 4 2t ns width mode 4 4t ns tcud high-/low-level t wtcuh , t wtcul other than mode 4 2t ns width mode 4 4t ns tclrud high-/low-level width t wcluh , t wclul 2t ns tcud setup time (vs. tiud - ) t stcu mode 3 t ns tcud hold time (vs. tiud - ) t htcu mode 3 t ns tiud setup time (vs. tcud) t s4tiu mode 4 2t ns tiud hold time (vs. tcud) t h4tiu mode 4 2t ns tiud & tcud cycle time t cyc other than mode 4 4 mhz t cyc4 mode 4 2 mhz remark t = t cyk = 1/f clk (f clk refers to the internal system clock frequency.)
m pd78363a, 78365a, 78366a, 78368a 77 other operations (t a = C40 to +85 ?c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol test conditions min. max. unit nmi high-/low-level width t wnih , t wnil 2 m s reset high-/low-level width t wrsh , t wrsl 1.5 m s intp0 high-/low-level t wi0h , t wi0l ts = t 250 ns width ts = 4t 1.0 m s ts = 8t 2.0 m s ts = 16t 4.0 m s intp1 high-/low-level t wi1h , t wi1l ts = t 250 ns width ts = 4t 1.0 m s ts = 8t 2.0 m s ts = 16t 4.0 m s intp2 high-/low-level t wi2h , t wi2l ts = t 250 ns width ts = 4t 1.0 m s intp3(ti) high-/low- t wi3h , t wi3l ts = t 250 ns level width ts = 4t 1.0 m s ts = 8t 2.0 m s ts = 16t 4.0 m s ts = 64t 16.0 m s ts = 128t 32.0 m s ts = 256t 64.0 m s intp4 high-/low-level t wi4h , t wi4l ts = t 250 ns width ts = 4t 1.0 m s ts = 8t 2.0 m s ts = 16t 4.0 m s remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency.) 2. ts refers to the input sampling frequency. intp0-intp4 can be selected to programmable.
m pd78363a, 78365a, 78366a, 78368a 78 a/d converter characteristics (t a = C40 to +85 ?c, v dd = +5 v 10 %, v ss = av ss = 0 v, v dd C 0.5 v av dd v dd ) parameter symbol test conditions min. typ. max. unit resolution 10 bit total error note 1 4.5 v av ref av dd 0.4 %fsr 3.4 v av ref av dd 0.7 %fsr quantization error 1/2 lsb conversion time t conv 62.5 ns t cyk < 80 ns 208 t cyk 80 ns t cyk 166.6 ns 169 t cyk sampling time t samp 62.5 ns t cyk < 80 ns 24 t cyk 80 ns t cyk 166.6 ns 20 t cyk zero-scale error note 1 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref av dd 1.5 4.5 lsb full-scale error note 1 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref av dd 1.5 4.5 lsb nonlinearity error note 1 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref av dd 1.5 4.5 lsb analog input voltage note 2 v ian C0.3 av ref + 0.3 v analog input impedance r an when not sampling 10 m w when sampling note 3 reference voltage av ref 3.4 av dd v av ref1 current ai ref 1.0 3.0 ma av dd supply current ai dd operating mode 2.0 6.0 ma a/d converter data ai dddr stop mode av dddr = 2.5 v 2 10 m a retention current av dddr = 5 v 10 % 10 50 m a notes 1. the quantization error is excluded. 2. when C0.3 v v ian 0 v, the conversion result becomes 000h. when 0 v < v ian < av ref , the conversion is performed with the 10-bit resolution. when av ref v ian +0.3 v, the conversion result becomes 3ffh. 3. the analog input impedance at the time of sampling is the same as the equivalent circuit shown below. (the values in the diagram are typ. values; they are not guaranteed values) analog input pin 1 k w 25 pf (input capacitance included) 4 pf
m pd78363a, 78365a, 78366a, 78368a 79 cautions1. when using the p70/ani0-p77/ani7 pins for both digital and analog inputs, the previ- ously described characteristics are not guaranteed. therefore, ensure that all of the eight p70/ani0-p77/ani7 pins are used either for analog input or digital input. 2. when using the p70/ani0-p77/ani7 pins as digital input, make sure to set that av dd = v dd , and av ss = v ss . ac timing test point 0.8 v dd or 2.2 v 0.2 v dd or 0.8 v 0.8 v dd or 2.2 v 0.2 v dd or 0.8 v v dd 0 v test point
m pd78363a, 78365a, 78366a, 78368a 80 read operation a8-a15 (output) ad0-ad7 (input/output) astb (output) rd (output) t wsth t sast t daid hi-z hi-z hi-z hi-z high-order address high-order address t cyk t hsta t fra t dstr t drid t dra t wrl t hrid low-order address (output) low-order address (output) data (input) (clk) write operation a8-a15 (output) ad0-ad7 (output) astb (output) wr (output) t wsth t sast high-order address high-order address t hsta t dstw t dwod t wwl low-order address (output) low-order address (output) data (output) (clk) t hwod t dwst undefined t sodw
m pd78363a, 78365a, 78366a, 78368a 81 serial operation t cysk t wskl t wskh t dsktx t srxsk t hskrx sck so si up/down counter (timer 4) input timing t wtiuh t stcu t htcu t wtiul t wtcul t wtcuh tiud tcud t wcluh t wclul tclrud tiud tcud t s4tiu t h4tiu t s4tiu t h4tiu
m pd78363a, 78365a, 78366a, 78368a 82 interrupt input timing t wnih t wnil 0.8 v dd 0.2 v dd nmi t winh t winl intpn 0.8 v dd 0.2 v dd remark n = 0 to 4 reset input timing t wrsh t wrsl 0.8 v dd 0.2 v dd reset
m pd78363a, 78365a, 78366a, 78368a 83 11. package drawing n a m f b 64 65 40 k l 80 pin plastic qfp (14 20) 80 1 25 24 41 g d c p detail of lead end s q 55 m i h j p80gf-80-3b9-2 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 0.8 0.35 0.10 0.15 20.0 0.2 0.929 0.016 0.039 0.031 0.006 0.031 (t.p.) 0.795 note m n 0.15 0.15 1.8 0.2 0.8 (t.p.) 0.006 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.014 0.551 0.8 0.2 0.031 p 2.7 0.106 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.008 ?.009
m pd78363a, 78365a, 78366a, 78368a 84 12. recommended soldering conditions these products should be soldered and mounted under the conditions recommended below. for details of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, please contact your nec sales representative. table 12-1. surface mount type soldering conditions m pd78363agf- -3b9: 80-pin plastic qfp (14 20 mm) m pd78365agf-3b9 : 80-pin plastic qfp (14 20 mm) m pd78366agf- -3b9: 80-pin plastic qfp (14 20 mm) m pd78368agf- -3b9: 80-pin plastic qfp (14 20 mm) soldering method infrared reflow vps wave soldering partial heating caution use of more than one soldering method should be avoided (except in the case of partial heating). recommended condition symbol ir35-00-3 vp15-00-3 ws60-00-1 C soldering conditions package peak temperature: 235 ?c, duration: 30 sec. max. (210 ?c or above) number of times: 3 max. package peak temperature: 215 ?c, duration: 40 sec. max. (200 ?c or above) number of times: 3 max. solder bath temperature: 260 ?c or less, time: 10 sec. max., number of times: 1, pre-heating temperature: 120 ?c max. (package surface temperature) pin temperature: 300 ?c or less duration: 3 sec. max. (per side of device)
m pd78363a, 78365a, 78366a, 78368a 85 appendix a. differences between m pd78366a and m pd78328 product name item 125 ns internal clock : 8 mhz, external clock : 16 mhz 250 ns minimum instruction execution time internal memory rom ram m pd78366a m pd78328 32k bytes 16k bytes 2k bytes 512 bytes 64k bytes (can be externally expanded) 8 bits 16 8 banks 115 111 ? 16-bit transfer/operation ? multiplication/division (16 bits 16 bits, 32 bits ? 16 bits) ? bit manipulation ? string memory space general-purpose registers number of basic instructions instruction set 11 (of which 8 are multiplexed with analog input) 41 ? 16-bit timer 3 ? 16-bit compare register 14 ? 16-bit capture/compare register 1 ? two output modes selectable mode 0, set-reset output : 6 channels toggle output : 1 channel mode 1, buffer output : 8 channels 4/8 (buffer output in 4-/8-bit units) 8-bit resolution pwm output: 1 channel ? sum-of-products operation (16 bits 16 bits + 32 bits) ? relative operation 14 (of which 8 are multiplexed with analog input) 49 ? 16-bit timer 5 ? 16-bit compare register 7 ? 16-bit capture register 3 ? 16-bit capture/compare register 2 ? two output modes selectable mode 0, set-reset output : 6 channels mode 1, buffer output : 6 channels ? 16-bit resolution pwm output: 1 channel 4 (buffer output in 4-bit units) 8-/9-/10-/12-bit resolution variable pwm output: 2 channels 10-bit resolution, 8 channels dedicated baud rate generator uart (with pin selection function) : 1 channel clocked serial interface/sbi : 1 channel ? external: 6, internal: 14 (2 multiplexed with external) ? 4 programmable priority levels real-time pulse unit real-time output port pwm unit a/d converter serial interface interrupt function test source pll control circuit package others input i/o dedicated baud rate generator uart : 1 channel clocked serial interface/sbi : 1 channel ? external: 4, internal: 17 ? 3 programmable priority levels ? three processing selectable (vectored interrupt/macro service/context switching) i/o lines internal clock : 16 mhz external clock : 8 mhz none internal: 1 provided (external 8 mhz ? internal: 16 mhz) none ? 80-pin plastic qfp (14 20 mm) ? 64-pin plastic shrink dip ? 64-pin plastic qfp (14 20 mm) ? watchdog timer ? standby functions (halt mode, stop mode)
m pd78363a, 78365a, 78366a, 78368a 86 host machine order code (product name) pc-9800 series ms-dos ibm pc/at and its pc dos compatible model hp9000 series 700 hp-ux sparc station sunos news news-os host machine order code (product name) pc-9800 series ms-dos tm ibm pc/at tm and its pc dos tm compatible model hp9000 series 700 tm hp-ux tm sparc station tm sunos tm news tm news-os tm appendix b. tools b.1 development tools the following development tools are available to support the system development using m pd78366a : language processor os supply media 3.5" 2hd m s5a13ra78k3 5" 2hd m s5a10ra78k3 3.5" 2hc m s7b13ra78k3 5" 2hc m s7b10ra78k3 dat m s3p16ra78k3 cartridge tape m s3k15ra78k3 (qic-24) m s3r15ra78k3 a relocatable assembler, that can be used commonly for the 78k/iii series products. since this assembler is provided with macro functions, it enhances the developmnt efficency. a structured assembler, that can explicitly describe the program control structure, is also supplied, so that the program productivity and maintainability can be improved. 78k/iii series relocatable assembler (ra78k3) this is a c compiler that can be commonly used for 78k/iii series. this program converts the program written in c language to object codes microcomputer can execute. when using this compiler, the 78k/iii series relocatable assembler (ra78k3) is necessary. os supply media 3.5" 2hd m s5a13cc78k3 5" 2hd m s5a10cc78k3 3.5" 2hc m s7b13cc78k3 5" 2hc m s7b10cc78k3 dat m s3p16cc78k3 cartridge tape m s3k15cc78k3 (qic-24) m s3r15cc78k3 78k/iii series c compiler (cc78k3) remark the operations of the relocatable assembler and c compiler are guaranteed only on the specified host machine and os described above.
m pd78363a, 78365a, 78366a, 78368a 87 this is a prom programmer that can program prom-contained single-chip microcontrollers in standalone mode or under control of a host machine when the accessory board and an optional programmer adapter are connected. it can also program representative proms from 256k-bit to 4m-bit models. prom programmer adapters that writes a program to the m pd78p368a on a general-purpose prom programmer such as the pg-1500. pa-78p368gf: for m pd78p368agf pa-78p368kl : for m pd78p368akl connects the pg-1500 and a host machine with a serial intrface and a parallel interface to control the pg-1500 from the host machine. pg-1500 pa-78p368gf pa-78p368kl pg-1500 controller in-circuit emulator that can be used to develop and debug application systems. connected to a host machine for debugging. i/o emulation board that emulates the peripheral functions of the target device such as i/o ports. emulation probe that connects the ie-78350-r to the target system. one conversion socket, ev-9200g-80, used to connect the target system is supplied as an accessory. program that controls the ie-78350-r on the host machine. it can automatically execute commands, enhancing debugging efficiency. ie-78350-r ie-78365-r-em1 ep-78365gf-r ie-78350-r control program (ie controller) ev-9200g-80 host machine order code (part number) pc-9800 series ms-dos ibm pc/at and pc dos compatible machines host machine order code (part number) pc-9800 series ms-dos ibm pc/at and pc dos compatible machines prom writing tools remark the operation of the pg-1500 controller is guaranteed only on the above host machine and os. debugging tools (when ie controller is used) remark the operation of the ie controller is guaranteed only on the above host machine and os. hardware software hardware software os supply media 3.5" 2hd m s5a13ie78365a 5" 2hd m s5a10ie78365a 3.5" 2hc m s7b13ie78365a 3.5" 2hc m s7b10ie78365a os supply media 3.5" 2hd m s5a13pg1500 5" 2hd m s5a10pg1500 3.5" 2hc m s7b13pg1500 3.5" 2hc m s7b10pg1500
m pd78363a, 78365a, 78366a, 78368a 88 development tool configuration (when using ie controller) host machine pc-9800 series ibm pc series ews software relocatable assembler ie controller c compiler pg-1500 controller built-in prom models m pd78p368agf m pd78p368akl + ++ programmer adapter pa-78p368gf pa-78p368kl pg-1500 rs-232-c rs-232c prom programmer ie-78350-r in-circuit emulator ie-78365-r-em1 i/o emulation board (optional) + emulation probe conversion socket for connecting the emulation probe and the target system note target system ep-78365gf-r ev-9200g-80 note a socket is provided with the emulation probe. remarks 1. host machine and pg-1500 can be directly connected by rs-232-c. 2. 3.5-inch fd represents the supply media of software in this figure.
m pd78363a, 78365a, 78366a, 78368a 89 ie-784000-r ie-78350-r-em-a ie-78365-r-em1 ep-78365gf-r ev-9200g-80 ie-70000-98-if-b ie-70000-98n-if ie-70000-pc-if-b ie-78000-r-sv3 integrated debugger (id78k3) device file (df78365) debugging tools (when integrated debugger is used) hardware software in-circuit emulation that can be used to develop and debug the application system. connected to a host machine for debugging. emulation board that emulates the peripheral functions of the target device such as i/o ports. i/o emulation board that emulates the peripheral functions of the target device such as i/o ports. emulation probe connecting the ie-784000-r to the target system. one conversion socket, ev- 9200g-80, used to connect the target system is supplied as an accessory. interface adapter to connect pc-9800 series (except notebook type personal computer) as the host machine. interface adapter and cable to connect pc-9800 series notebook type personal computer as the host machine. interface adapter and cable to connect ibm pc as the host machine. interface board to connect ews as the host machine. program controlling the in-circuit emulator for the 78k/iii series. used in combination with a device file (df78365). can debug a program coded in the c language, structured assembly language, or assembly language at source program level. can also split the screen of the host machine into windows on each of which information is displayed, enhancing debugging efficiency. host machine order code (part number) os supply media pc-9800 series ms-dos 3.5" 2hd m saa13id78k3 windows tm 5" 2hd m saa10id78k3 ibm pc/at and compatible pc dos 3.5" 2hc m sab13id78k3 machines ( japanese windows ) windows 5" 2hc m sab10id78k3 ibm pc/at and compatible 3.5" 2hc m sbb13id78k3 machines ( english windows ) 5" 2hc m sbb10id78k3 file containing information peculiar to device. use in combination with an assembler (ra78 k3), c compiler (cc78k3), and integrated debugger (id78k3). host machine order code (part number) os supply media pc-9800 series ms-dos 3.5" 2hd m s5a13df78365 5" 2hd m s5a10df78365 ibm pc/at and compatible pc dos 3.5" 2hc m s7b13df78365 machines 5" 2hc m s7b10df78365 + + remark the operation of the integrated debugger and device file is guaranteed only on the above host machine and os.
m pd78363a, 78365a, 78366a, 78368a 90 development tool configuration (when using integrated debugger) host machine pc-9800 series ibm pc/at ews ie-70000-98-if-b ie-70000-98n-if ie-70000-pc-if-b software relocatable assembler integrated debugger device file c compiler pg-1500 controller built-in prom models m pd78p368agf m pd78p368akl + ++ programmer adapter pa-78p368gf pa-78p368kl prom programmer pg-1500 ie-784000-r in-circuit emulator ie-78350-r-em-a emulation board (optional) ie-78365-r-em1 i/o emulation board (optional) + + emulation probe conversion socket for connecting the emulation probe and the target system note target system ep-78365gf-r ev-9200g-80 rs-232c note a socket is provided with the emulation probe. remarks 1. desk top-type pc represents host machine in this figure. 2. 3.5-inch fd represents the supply media of software in this figure.
m pd78363a, 78365a, 78366a, 78368a 91 b.2 embedded software the following embedded software is available for enhancing the efficiency of program development and maintenance. real-time os real-time os (rx78k/iii) note rx78k/iii is intended to implement a multi-tasking environment for use in the control field where real-time capability is a must. it can allocate the idle time of the cpu to other processing to improve the overall performance of the system. rx78k/iii provides system calls conforming to the m itron specification. the rx78k/iii package supplies a tool (configurator) to create the nucleus of rx78k/iii and multiple information tables. host machine order code (part number) os supply media pc-9800 series ms-dos 3.5" 2hd pending 5" 2hd pending ibm pc/at and compatible pc dos 3.5" 2hc pending machines 5" 2hc pending note under development caution before purchasing this product, you are requested to conclude a contract licensing use by filling out a specified form. remark when using the rx78k/iii real-time os, the ra78k3 assembler package (optional) is necessary.
m pd78363a, 78365a, 78366a, 78368a 92 fuzzy inference development support system note under development fuzzy knowledge data creation tool (fe9000, fe9200) translator (ft78k3) note fuzzy inference module (fi78k/iii) note fuzzy inference debugger (fd78k/iii) program that supports input/editing and evaluation (simulation) of fuzzy knowledge (fuzzy rules and membership functions). host machine order code (part number) os supply media pc-9800 series ms-dos 3.5" 2hd m s5a13fe9000 5" 2hd m s5a10fe9000 ibm pc/at and compatible pc dos 3.5" 2hc m s7b13fe9200 machines windows 5" 2hc m s7b10fe9200 program that converts the fuzzy knowledge data obtained by using the fuzzy knowledge data creation tool into assembler source program for the ra78k/iii. host machine order code (part number) os supply media pc-9800 series ms-dos 3.5" 2hd m s5a13ft78k3 5" 2hd m s5a10ft78k3 ibm pc/at and compatible pc dos 3.5" 2hc m s7b13ft78k3 machines 5" 2hc m s7b10ft78k3 program that executes fuzzy inference when linked with the fuzzy knowledge data converted by the translator. host machine order code (part number) os supply media pc-9800 series ms-dos 3.5" 2hd m s5a13fi78k3 5" 2hd m s5a10fi78k3 ibm pc/at and compatible pc dos 3.5" 2hc m s7b13fi78k3 machines 5" 2hc m s7b10fi78k3 support software that evaluates and adjusts the fuzzy knowledge data at the hardware level by using an in-circuit emulator. host machine order code (part number) os supply media pc-9800 series ms-dos 3.5" 2hd m s5a13fd78k3 5" 2hd m s5a10fd78k3 ibm pc/at and compatible pc dos 3.5" 2hc m s7b13fd78k3 machines 5" 2hc m s7b10fd78k3 +
m pd78363a, 78365a, 78366a, 78368a 93 [memo]
m pd78363a, 78365a, 78366a, 78368a 94 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd78363a, 78365a, 78366a, 78368a 95 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd78363a, 78365a, 78366a, 78368a 2 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. lisence not needed : m pd78365a the customer must judge the need for license : m pd78363a, 78366a, 78368a

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